Abstract: A power device includes a semiconductor substrate having first and second current carrying terminals on respective first and second opposing surfaces thereof. A silicided polysilicon temperature sensor and silicided polysilicon gate electrode are provided on the first surface. A source region of first conductivity type and a shielding region of second conductivity type are provided in the semiconductor substrate. The shielding region forms a P-N rectifying junction with the source region, and extends between the silicided polysilicon temperature sensor and the second current carrying terminal. A field oxide insulating region is provided, which extends between the shielding region and the silicided polysilicon temperature sensor.

Abstract: A power device includes a packaged semiconductor switch containing first and second series-connected insulated-gate transistors, first and second control terminals electrically connected to the first and second insulated-gate transistors, respectively, first and second current carrying terminals electrically connected to the first and second insulated-gate transistors, respectively, and a voltage-monitoring terminal electrically connected to an internal node shared by first and second current carrying regions within the first and second insulated-gate transistors, respectively. The first and second control terminals can be electrically connected to a gate of the first insulated-gate transistor and a gate of the second insulated-gate transistor, respectively; and the first and second current carrying terminals can be electrically connected to a source of the first insulated-gate transistor and a drain (or collector) of the second insulated-gate transistor.

Abstract: A vertical insulated-gate field effect transistor includes a semiconductor substrate and a gate electrode on a first surface thereof. This gate electrode has a plurality of eight (or more) sided openings extending therethrough. Each of these openings has eight (or more) sidewalls, including a first plurality of sidewalls that are flat relative to a center of the opening and second plurality of sidewalls that are either flat or concave relative to the center of the opening. A source electrode is also provided, which extends into the openings. This source electrode may ohmically contact a source region within the semiconductor substrate. If the field effect transistor is a JBSFET, the source electrode may also form a Schottky rectifying junction with a drift region within the semiconductor substrate.

Abstract: A monolithically-integrated AC switch includes a semiconductor substrate having first and second insulated-gate field effect transistors therein, which contain first and second spaced-apart and independently-controllable source terminals extending adjacent a first surface of the semiconductor substrate, yet share a common drain electrode extending adjacent a second surface of the semiconductor substrate. According to some of these embodiments of the invention, the first and second insulated-gate field effect transistors include respective first and second independently-controllable gate electrodes, which extend adjacent the first surface. The first and second insulated-gate field effect transistors may be configured as first and second vertical power MOSFETs, respectively. The semiconductor substrate may also include at least one edge termination region therein, which extends between the first and second vertical power MOSFETs.

Abstract: An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

Abstract: An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.

Abstract: Disclosed herein are techniques of manufacturing semiconductor devices having a positive-bevel termination and/or a negative-bevel termination. In a particular example, techniques are disclosed for manufacture of a chip-size SiC device having an orthogonal positive-bevel termination used for the reverse blocking junction. The edge termination may be formed, for example, by cutting across a SiC wafer with a V-shaped dicing tool or blade. The cut may be performed by any suitable dicing tool. The cut may be across a p-n junction for forming positive-bevel termination. Subsequently, a surface of the termination may be etched for removing damage caused by the cutting process.

Abstract: Disclosed herein are solid state fault isolation devices and methods. According to one or more embodiments, a semiconductor current fault controlled device is provided. The device includes a semiconductor substrate of N-type conductivity. The substrate has opposed major surfaces. An anode region of P-type conductivity is formed in one major surface. A P-type buried layer is formed in a first portion of the other major surface. A junction field-effect transistor (JFET) is formed in a second portion of the other major surface. A P-type top layer is formed in the JFET and forms a channel defined by an overlap between the P-type buried layer and the P-type top layer. The channel laterally extends to the semiconductor substrate from a cathode region and being shielded from the anode region.

Abstract: In one embodiment, the present invention is a method for reducing the peak-to-average power ratio (PAPR) of a multi-carrier modulated symbol, such as an orthogonal frequency division multiplexed (OFDM) symbol. The method first transforms a set of data symbols into a multi-carrier modulated symbol. The method then uses the multi-carrier modulated symbol and a gradient-descent algorithm to generate a set of symbols for PAPR-reduction tones. The data symbols and the PAPR-reduction symbols are then transformed to generate an updated multi-carrier modulated symbol. The PAPR-reduction symbols are iteratively updated until a terminating condition occurs (e.g., an acceptable PAPR is achieved for the multi-carrier modulated symbol).

Abstract: In one embodiment, the present invention is a method for reducing the peak-to-average power ratio (PAPR) of a multi-carrier modulated symbol, such as an orthogonal frequency division multiplexed (OFDM) symbol. The method first transforms a set of data symbols into a multi-carrier modulated symbol. The method then uses the multi-carrier modulated symbol and a gradient-descent algorithm to generate a set of symbols for PAPR-reduction tones. The data symbols and the PAPR-reduction symbols are then transformed to generate an updated multi-carrier modulated symbol. The PAPR-reduction symbols are iteratively updated until a terminating condition occurs (e.g., an acceptable PAPR is achieved for the multi-carrier modulated symbol).

Abstract: Methods of forming power semiconductor devices include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is formed on the first surface. Base and base shielding region dopants are implanted into the transition region using the gate electrode as an implant mask. A plurality of annealing steps are performed so that the base shielding region dopants are driven in laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width.

Abstract: Methods of forming vertical power devices include the steps of forming a lateral-channel MOSFET having a base region of second conductivity type within the semiconductor substrate and a source region of first conductivity type within the base region. A trench is also formed in the semiconductor substrate. The trench has sidewalls that define an interface with the source and base regions. The sidewalls of the trench are lined with a trench insulating layer and an electrically conductive region is formed on the trench insulating layer. An upper portion of the trench insulating layer is removed to expose a portion of the base region extending along the interface. A source electrode is then formed that ohmically contacts the source region, the exposed portion of the base region and the electrically conductive region, which operates as a trench-based electrode.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and first and second transition regions of first conductivity type that extend between the drift region and a first surface of the semiconductor substrate. Each of the first and second transition regions has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface. First and second shielding regions of second conductivity type are provided in the drift region and define respective P-N junctions with the first transition region. The shielding regions extending laterally towards each other in a manner that constricts a neck of the first transition region to a minimum width at a second depth relative to the first surface. An anode electrode is provided. The anode electrode that extends on the first surface of the semiconductor substrate and defines a Schottky rectifying junction with the second transition region.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and a transition region that extends between the drift region and a first surface of the semiconductor substrate. The transition region has a vertically retrograded doping profile therein that peaks at a first depth relative to the first surface. An insulated gate electrode is provided that extends on the first surface and has first and second opposing ends. First and second base regions of second conductivity type are provided in the substrate. The first and second base regions are self-aligned to the first and second ends of the insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of the transition region extending adjacent the first surface. First and second source regions are provided in the first and second base regions, respectively.

Abstract: Power MOSFET devices provide highly linear transfer characteristics (e.g., Id v. Vg) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Abstract: A power field effect transistor utilizes a retrograded-doped transition region to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition region and contribute to depletion of the transition region during both forward on-state conduction and reverse blocking modes of operation. In a vertical embodiment, the transition region has a peak first conductivity type dopant concentration at a first depth relative to a surface on which gate electrodes are formed. A product of the peak dopant concentration and a width of the transition region at the first depth is preferably in a range between 1×1012 cm−2 and 7×1012 cm−2.

Abstract: Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and first and second transition regions of first conductivity type that extend between the drift region and a first surface of the semiconductor substrate. Each of the first and second transition regions has a vertically retrograded first conductivity type doping profile therein that peaks at a first depth relative to the first surface. First and second shielding regions of second conductivity type are provided in the drift region and define respective P-N junctions with the first transition region. The shielding regions extending laterally towards each other in a manner that constricts a neck of the first transition region to a minimum width at a second depth relative to the first surface. An anode electrode is provided. The anode electrode that extends on the first surface of the semiconductor substrate and defines a Schottky rectifying junction with the second transition region.

Abstract: Methods of forming vertical power devices include the steps of forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively. Steps are also performed to form a UMOSFET in the mesa and form first and second base shielding regions of second conductivity type that extend into the mesa and are self-aligned with the first and second opposing sidewalls.

Abstract: Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region.