Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.

Abstract: Power semiconductor devices include a semiconductor substrate having a face thereon and a buried electrically insulating layer extending laterally in the semiconductor substrate and having an opening therein. A drift region of first conductivity type is also provided in the semiconductor substrate. To improve breakdown voltage characteristics, the drift region extends through the opening in the buried electrically insulating layer and has a first conductivity type doping concentration therein that is established at a level sufficient to generate a first conductivity type charge density of between 1.times.10.sup.12 cm.sup.-2 and 5.times.10.sup.13 cm.sup.-2 across the opening.

Abstract: Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate.

Abstract: Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (C.sub.GD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: Semiconductor switching devices having buried gate electrodes include a substrate, a drift region of first conductivity type (e.g., N-) extending to a face of the substrate and a first insulated gate electrode buried in the drift region. The first insulated gate electrode extends laterally in the substrate in spaced relation to the face. A second gate electrode is also provided on the face at a location extending opposite the first insulated gate electrode. A base region of second conductivity type (e.g., P) is also provided in the substrate, between the second gate electrode and an upper surface of the first insulated gate electrode. Similarly, an emitter region of first conductivity type (e.g., N+) is provided between the first face and the upper surface of the first insulated gate electrode. The base region is defined so that respective P-N junctions are formed with the emitter and drift regions.

Abstract: A silicon carbide switching device having near ideal electrical characteristics includes an electrical insulator with an electrical permittivity greater than about ten times the permittivity of free space (.epsilon..sub.o) and more preferably greater than about fifteen times the permittivity of free space, as a gate electrode insulating region. The use of electrical insulators having high electrical permittivities relative to conventional electrical insulators such as silicon dioxide significantly improves the breakdown voltage and on-state resistance characteristics of a silicon carbide switching device to the point of near ideal characteristics, as predicted by theoretical analysis. Thus, the preferred advantages of using silicon carbide, instead of silicon, can be more fully realized.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: A depleted base transistor with high forward voltage blocking capability includes cathode and anode regions on opposite faces of a semiconductor substrate, a base region therebetween, a rectifying junction for depleting a portion of the base region of majority free carriers and an insulated gate electrode in a trench for modulating the conductivity of the depleted portion of the base region. The regions are formed as a vertical stack of semiconductor layers with the anode region (e.g., P+) as the bottom layer, the buffer region (e.g., N+) on the anode region, the drift region/e.g., N-) on the buffer region, the blocking voltage enhancement region (e.g., N-) on the drift region and the cathode region (e.g., N+) as the top layer on the blocking voltage enhancement region.

Abstract: A gate-controlled bipolar transistor with buried collector includes a wide base bipolar transistor in a semiconductor substrate having a trench at a face thereof. A dual-channel insulated-gate field effect transistor (IGFET) is also included adjacent a sidewall of the trench for providing gated turn-on and turn-off control of the bipolar transistor. The bipolar transistor includes a buried collector region at a bottom of the trench, which is electrically connected to a cathode contact at the face. An emitter of the transistor is electrically connected to an anode contact at an opposing face of the substrate. For turn-on, the base of the bipolar transistor is electrically connected to the cathode contact upon the application of a gate bias signal to the IGFET. By electrically connecting the base to the cathode contact, forward conduction can be established once the anode contact is appropriately biased relative to the cathode contact.

Abstract: A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts.

Abstract: A trench gate lateral MOSFET structure has the voltage supported along side walls and the bottom surface of the trench. With narrow source and drain mesa regions that are optimally doped, a uniform electric field is obtained vertically in the mesa regions and horizontally at the bottom of the trench, allowing a relative high doping level in an N-drift region resulting in specific on-resistances well below those of conventional lateral MOSFETs at a high breakdown voltage.

Abstract: A switching device including four layers (20), (22), (42) and (44) and a gate electrode (32). In its blocking state the switching device operates as a conventional thyristor. The device is turned off by reducing the effective resistance of the upper base region (42) by applying a negative voltage to the gate (32).

Abstract: A field controlled thyristor having its base doped more lightly near the gate than near the anode achieves a low forward voltage drop, high blocking gain, and fast switching speed at any given forward blocking voltage rating. Although the high resistivity region around the gate area allows the device to pinch off anode current flow at zero gate bias due to the gate junction inherent potential, a small forward gate voltage can trigger the device into conduction. The high resistivity of the channel area between gates provides DC blocking gains greater than 60. The device can be fabricated using conventional planar processing techniques.

Abstract: A field-controlled bipolar transistor characterized by a bidirectional voltage blocking capability between the collector and emitter electrodes is described as comprising a semiconductor substrate with base, emitter and collector regions formed in the semiconductor substrate with the base region of one conductivity type and the emitter and collector regions of opposite conductivity type. A gate region, also of opposite conductivity type, is formed in the substrate and positioned with respect to the emitter and collector regions so that when the junction formed between the gate region and the substrate is reverse-biased, a depletion region forms which pinches off current flow between the emitter and collector regions thereby providing a transistor that is capable of blocking high voltages in both forward and reverse directions while having normal bipolar transistor characteristics in the forward direction.

Abstract: A thyristor is protected against voltage breakover turn-on failure by selective control of the minority charge carrier lifetime in the base region and in the gate region to establish a predictable location of the voltage breakover turn-on in the gate region. Carrier lifetime modification in the selected gate region is achieved by shielding the gate region during electron irradiation of the high-lifetime silicon substrate to protect against lifetime-killing radiation defect centers, by annealling the gate region after electron irradiation to a temperature threshold known to eliminate the radiation-induced defects, or by introducing lifetime killing defects, such as gold or platinum, external to the gate region, typically by selective diffusion or localized ion implantation.

Abstract: An electric field-controlled thyristor having improved voltage blocking characteristics comprises a semiconductor substrate with a cathode region in one major surface and interdigitated anode and gate regions in the other major surface. The thyristor includes a single high voltage junction which is capable of blocking voltages of either positive or negative polarity by the application of a control voltage, which is a fraction of the blocking voltage, between the anode and gate regions.

Abstract: Geometrical design criteria are disclosed for a Gate Modulated BiPolar Transistor, or GAMBIT, which is a three terminal variable negative resistance device. The GAMBIT is a planar, interdigited, integrated device whose electrical characteristics show a voltage controlled negative resistance between two of its terminals. The magnitude of the negative resistance is controlled by the variation of the applied bias to the third terminal.

Abstract: A Gate Modulated BiPolar Transistor, or GAMBIT, is a three terminal negative resistance device. A load is connected between the emitter and collector terminals and the magnitude of the negative resistance is controlled by the voltage on the gate terminal. An increase in the output voltage modulates the resistance of the gate which decreases the output current.