Abstract: Methods of forming vertical MOSFETs include forming a base region of second conductivity type in a semiconductor substrate having a drift region of first conductivity type therein that forms a P-N junction with the base region. A source region of first conductivity type is formed in the base region and a deep trench, having a first sidewall that extends adjacent the base region, is formed in the substrate. The deep trench is lined with a first electrically insulating layer. The deep trench is then refilled with a trench-based source electrode. The trench-based source electrode is selectively etched to define a shallow trench therein and expose a first portion of the first electrically insulating layer that extends on the first sidewall of the deep trench. The first portion of the first electrically insulating layer is selectively etched to expose an upper portion of the first sidewall of the deep trench and reveal the base region.

Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Abstract: Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.

Abstract: Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a first direction. A plurality of buried insulated source electrodes are formed in the in the plurality of deep stripe-shaped trenches. A plurality of insulated gate electrodes are also provided that extend in parallel across the plurality of semiconductor mesas and into shallow trenches defined within the plurality of buried insulated source electrodes. A surface source electrode is provided on the substrate. The surface source electrode is electrically connected to each of the buried source electrodes at multiple locations along the length of each buried source electrode and these multiple connections decrease the effective source electrode resistance and enhance device switching speed.

Abstract: Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.

Abstract: MOSFET embodiments of the present invention provide highly linear transfer characteristics (e.g., Id v. Vg) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a MOSFET having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is preferably provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports separate and simultaneous linear and current saturation modes.

Abstract: Vertical power devices include a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein. A quad arrangement of trenches are provided that extend into the first surface of the semiconductor substrate and define a drift region mesa therebetween. A base region of second conductivity type is included. The base region extends into the drift region and forms a first P-N rectifying junction therewith. A source region of first conductivity type is provided that extends into the base region and forms a second P-N rectifying junction therewith. A quad arrangement of insulated electrodes is provided in the quad arrangement of trenches. An insulated gate is provided on the drift region mesa. A source electrode is also provided that extends on the first surface. The source electrode is electrically connected to the source and base regions and to the quad arrangement of insulated electrodes.

Abstract: Power MOSFET devices provide highly linear transfer characteristics (e.g., Id v. Vg) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Abstract: A power MOSFET includes a semiconductor substrate having a drift region therein and a transition region that extends between the drift region and a first surface of the semiconductor substrate. The transition region has a vertically retrograded doping profile therein that peaks at a first depth relative to the first surface. An insulated gate electrode is provided that extends on the first surface and has first and second opposing ends. First and second base regions of second conductivity type are provided in the substrate. The first and second base regions are self-aligned to the first and second ends of the insulated gate electrode, respectively, and form respective P-N junctions with opposing sides of an upper portion of the transition region extending adjacent the first surface. First and second source regions are provided in the first and second base regions, respectively.

Abstract: A power field effect transistor utilizes a retrograded-doped transition region to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition region and contribute to depletion of the transition region during both forward on-state conduction and reverse blocking modes of operation. In a vertical embodiment, the transition region has a peak first conductivity type dopant concentration at a first depth relative to a surface on which gate electrodes are formed. A product of the peak dopant concentration and a width of the transition region at the first depth is preferably in a range between 1×1012 cm−2 and 7×1012 cm−2.

Abstract: Vertical power devices include a semiconductor substrate having a first surface thereon and a drift region of first conductivity type therein. A quad arrangement of trenches are provided that extend into the first surface of the semiconductor substrate and define a drift region mesa therebetween. A base region of second conductivity type is included. The base region extends into the drift region and forms a first P-N rectifying junction therewith. A source region of first conductivity type is provided that extends into the base region and forms a second P-N rectifying junction therewith. A quad arrangement of insulated electrodes is provided in the quad arrangement of trenches. An insulated gate is provided on the drift region mesa. A source electrode is also provided that extends on the first surface. The source electrode is electrically connected to the source and base regions and to the quad arrangement of insulated electrodes.

Abstract: Vertical power devices include a semiconductor substrate having a drift region of first conductivity type therein and first and second stripe-shaped trenches that extend in the semiconductor substrate and define a drift region mesa therebetween. First and second insulated source electrodes are provided in the first and second stripe-shaped trenches, respectively. A UMOSFET, comprising a third trench that is shallower than the first and second stripe-shaped trenches, is provided in the drift region mesa.

Abstract: Packaged power devices include an electrically conductive flange having a slot therein and an electrically conductive substrate mounted within the slot. A dielectric layer is provided on the electrically conductive substrate and a gate electrode strip line is patterned on the dielectric layer. The gate electrode strip line extends opposite the electrically conductive substrate. A vertical MOSFET is also provided. The vertical MOSFET has a source electrically coupled and mounted to a first portion of the flange located outside the slot and a gate electrode electrically coupled and mounted to a first end of the gate electrode strip line.

Abstract: Integrated power devices include a plurality of field effect transistor unit cells and a Faraday shield layer that reduces parasitic gate-to-drain capacitance (Cgd) and concomitantly improves high frequency switching performance. These power devices may include a field effect transistor in an active portion of a semiconductor substrate and a gate electrode that is electrically connected to a gate of the field effect transistor. A Faraday shield layer is provided between at least a first portion of the gate electrode and a drain of the field effect transistor in order to capacitively decouple the first portion of the gate electrode from the drain. The gate electrode and drain typically extend adjacent opposing faces of the semiconductor substrate. The Faraday shield layer is preferably electrically connected to a source of the field effect transistor and provides edge termination.

Abstract: Integrated power semiconductor devices having improved high frequency switching performance, improved edge termination characteristics and reduced on-state resistance include GD-UMOSFET unit cells with upper trench-based gate electrodes and lower trench-based source electrodes. The use of the trench-based source electrode instead of a larger gate electrode reduces the gate-to-drain capacitance (CGD) of the UMOSFET and improves switching speed by reducing the amount of gate charging and discharging current that is needed during high frequency operation.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.

Abstract: Vertical MOSFETs include a semiconductor substrate having a plurality of semiconductor mesas therein that are separated by a plurality of deep stripe-shaped trenches. These stripe-shaped trenches extend in parallel and lengthwise across the substrate in a first direction. A plurality of buried insulated source electrodes are formed in the in the plurality of deep stripe-shaped trenches. A plurality of insulated gate electrodes are also provided that extend in parallel across the plurality of semiconductor mesas and into shallow trenches defined within the plurality of buried insulated source electrodes. A surface source electrode is provided on the substrate. The surface source electrode is electrically connected to each of the buried source electrodes at multiple locations along the length of each buried source electrode and these multiple connections decrease the effective source electrode resistance and enhance device switching speed.

Abstract: Silicon carbide power devices having trench-based charge coupling regions include a silicon carbide substrate having a silicon carbide drift region of first conductivity type (e.g., N-type) and a trench therein at a first face thereof. A uniformly doped silicon carbide charge coupling region of second conductivity type (e.g., an in-situ doped epitaxial P-type region) is also provided in the trench. This charge coupling region forms a P-N rectifying junction with the drift region that extends along a sidewall of the trench. The drift region and charge coupling region are both uniformly doped at equivalent and relatively high net majority carrier doping concentrations (e.g., 1×1017 cm−3) so that both the drift region and charge coupling region can be depleted substantially uniformly when blocking reverse voltages.

Abstract: Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the substrate so that the trench has a bottom which extends opposite the drift region and a sidewall which extends from the drift region to the face. The sidewall may extend orthogonal to the face or at an angle greater than 90°. A preferred insulated gate electrode is formed by lining the face and trench with a gate electrode insulating layer and then forming a conductive layer on the gate electrode insulating layer. The conductive layer is preferably formed to extend opposite a portion of the face adjacent to the trench and into the trench. A step is then performed to pattern the conductive layer to define a T-shaped or Y-shaped gate electrode which fills the trench and also extends opposite the face at a location adjacent the trench.

Abstract: Power semiconductor devices having tapered insulating regions include a drift region of first conductivity type therein and first and second trenches in the substrate. The first and second trenches have first and second opposing sidewalls, respectively, that define a mesa therebetween into which the drift region extends. An electrically insulating region having tapered sidewalls is also provided in each of the trenches. The tapered thickness of each of the electrically insulating regions enhances the degree of uniformity of the electric field along the sidewalls of the trenches and in the mesa and allows the power device to support higher blocking voltages despite a high concentration of dopants in the drift region. In particular, an electrically insulating region lines the first sidewall of the first trench and has a nonuniform thickness Tins(y) in a range between about 0.5 and 1.