Patents by Inventor Jaynal A. Molla

Jaynal A. Molla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941210
    Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mali Mahalingam, Colby Rampley
  • Publication number: 20180082915
    Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.
    Type: Application
    Filed: September 19, 2016
    Publication date: March 22, 2018
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: LAKSHMINARAYAN VISWANATHAN, JAYNAL A. MOLLA, DAVID ABDO, MALI MAHALINGAM, CARL D'ACOSTA
  • Patent number: 9922894
    Abstract: Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique structural features are disclosed. In one embodiment, a method for fabricating an air cavity package includes the step or process of forming a first metal particle-containing precursor layer between a base flange and a window frame positioned over the base flange. A second metal particle-containing precursor layer is further formed between the base flange and a microelectronic device positioned over the base flange. The metal particle-containing precursor layers are sintered substantially concurrently at a maximum processing temperature less than melt point(s) of metal particles within the layers to produce a first sintered bond layer from the first precursor layer joining the window frame to the base flange and to produce a second sintered bond layer from the second precursor layer joining the microelectronic device to the base flange.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: March 20, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, David Abdo, Mali Mahalingam, Carl D'Acosta
  • Patent number: 9875987
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: January 23, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20180012815
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Application
    Filed: September 20, 2017
    Publication date: January 11, 2018
    Inventors: LI LI, Jaynal A. Molla, Lakshminarayan Viswanathan
  • Patent number: 9799580
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Li Li, Jaynal A. Molla, Lakshminarayan Viswanathan
  • Publication number: 20170278763
    Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: Li LI, Jaynal A. MOLLA, Lakshminarayan VISWANATHAN
  • Publication number: 20170263529
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Application
    Filed: May 30, 2017
    Publication date: September 14, 2017
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9698116
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: July 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9589860
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9538659
    Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mahesh K. Shah
  • Publication number: 20160365323
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 15, 2016
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9425161
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20160126206
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20160099199
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 7, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20150333031
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. MAHALINGAM, DAVID F. ABDO, JAYNAL A. MOLLA
  • Patent number: 9099567
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20150146399
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20150055310
    Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, Jaynal A. Molla, Mahesh K. Shah
  • Patent number: 7829980
    Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: November 9, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Jaynal A. Molla, Eric J. Salter