Patents by Inventor Jaynal A. Molla

Jaynal A. Molla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6936763
    Abstract: Shielded electronic integrated circuit apparatus (5) includes a substrate (10), with an eletronic integrated circuit (15) formed thereon, and a dielectric region (12) positioned on the electronic integrated circuit. The dielectric region and the substrate are substantially surrounded by lower and upper magnetic material regions (26, 30), deposited using electrochemical deposition, and magnetic material layers on each side (32, 34). Each of the lower and upper magnetic material regions preferably include a glue layer (36, 40), a seed layer (28, 24), and an electrochemically deposited magnetic material layer (26, 30). Generally, the electrochemically deposited magnetic material layer can be conveniently deposited by electroplating.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: August 30, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Nicholas D. Rizzo, Mark A. Durlam, Michael J. Roll, Kelly Kyler, Jaynal A. Molla
  • Patent number: 6927072
    Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: August 9, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
  • Publication number: 20050164413
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 28, 2005
    Inventors: Thomas Meixner, Gregory Grynkewich, Jaynal Molla, J. Ren, Richard Williams, Brian Butcher, Mark Durlam
  • Publication number: 20050158992
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Application
    Filed: March 16, 2005
    Publication date: July 21, 2005
    Inventors: Mark Durlam, Jeffrey Baker, Brian Butcher, Mark Deherrera, John D'Urso, Earl Fuchs, Gregory Grynkewich, Kelly Kyler, Jaynal Molla, J. Ren, Nicholas Rizzo
  • Publication number: 20050095855
    Abstract: Methods and compositions are provided for the electroless deposition of NiFe on a work piece. A deposition solution for use in electroless deposition of NiFe on a work piece is formed from a nickel ion source, a ferrous iron source, a complexing agent, a reducing agent, and a pH adjusting agent. The deposition solution is substantially free from alkali metal ions. A method for fabricating a flux concentrating system for use in a magnetoelectronics device begins by providing a work piece and forming an insulating material layer overlying the work piece. A trench is formed in an insulating layer and a barrier layer is deposited within the trench. A NiFe cladding layer is deposited overlying the barrier layer. After depositing the NiFe cladding layer, the insulating material layer proximate to the trench has a concentration of alkali metal ions less than about 1×1011 atoms/cm2.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 5, 2005
    Inventors: John D'urso, Jaynal Molla, Kelly Kyler
  • Patent number: 6885074
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
  • Publication number: 20040175845
    Abstract: A method of forming a magnetic device, especially the digit line of a magnetic random access memory (MRAM) device is disclosed. The digit line includes a stack of materials that includes a barrier layer, a seed layer and a soft magnetic layer that is electrochemically deposited. Preferably, the barrier layer and the seed layer are formed by physical vapor deposition (PVD) and the soft magnetic layer is formed by electroless plating. In one embodiment, the barrier layer includes tantalum, the seed layer includes ruthenium and the soft magnetic layer includes nickel and iron.
    Type: Application
    Filed: March 3, 2003
    Publication date: September 9, 2004
    Inventors: Jaynal A. Molla, John J. D'Urso, J. Jack Ren
  • Publication number: 20040099908
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
  • Publication number: 20040000415
    Abstract: A shielded electronic integrated circuit apparatus (5) comprising a substrate (10) with an electronic integrated circuit (15) formed thereon, a dielectric region (12) positioned on the substrate and the electronic integrated circuit wherein the dielectric region and the substrate are substantially surrounded by a magnetic material region (26, 30) deposited using electrochemical deposition and wherein the electronic integrated circuit is shielded from electromagnetic radiation.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Nicholas D. Rizzo, Mark A. Durlam, Michael J. Roll, Kelly Kyler, Jaynal A. Molla
  • Publication number: 20030170976
    Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
  • Patent number: 6137213
    Abstract: A field emission device (100, 150) includes a cathode plate (102, 180) having electron emitters (116), an anode plate (104, 170) having a phosphor (107, 207, 307, 407) activated by electrons (119) emitted by electron emitters (116), and a vacuum bridge focusing structure (118, 158, 218, 318) for focusing electrons (119) emitted by electron emitters (116). Vacuum bridge focusing structure (118, 158, 218, 318) has landings (121, 122, 221, 322), which are attached to cathode plate (102, 180), and further has bridges (120, 220, 320), which extend above and beyond landings (121, 122, 221, 322, 421) to provide a self-supporting structure that is spaced apart from cathode plate (102, 180).
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: October 24, 2000
    Assignee: Motorola, Inc.
    Inventors: Curtis D. Moyer, Peter A. Smith, Robert H. Reuss, Troy A. Trottier, Steven A. Voight, Diane A. Carrillo, Kevin J. Nordquist, Jaynal A. Molla, David W. Jacobs, Kathleen A. Tobin
  • Patent number: 5910641
    Abstract: An electrically conductive adhesive film having a pattern of microscopic elongate metal particles which extend from one surface to the other to provide an interconnection between confronting conductive metal pads abutting the surface. The particles have sharp ends to penetrate the oxide coating on the conductive metal pads of an electronic module when force is applied to press the module against the film.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: June 8, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Jaynal A. Molla
  • Patent number: 5798050
    Abstract: A process for fabrication of an electrically conductive adhesive film having a pattern of microscopic elongate metal particles which extend from one surface to the other to provide an interconnection between confronting conductive metal pads abutting the surface. The particles have sharp ends to penetrate the oxide coating on the conductive metal pads of an electronic module when force is applied to press the module against the film.
    Type: Grant
    Filed: July 17, 1997
    Date of Patent: August 25, 1998
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Jaynal A. Molla
  • Patent number: 5435057
    Abstract: Polymeric subcomposites of a circuit board are interconnected by metallic dendrites on electrical contact pads whereby electrical contact pads of one or the subcomposites are larger widthwise than electrical contact pads of the other subcomposite.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: July 25, 1995
    Assignee: International Business Machines Corporation
    Inventors: Perminder S. Bindra, Ross D. Havens, Voya R. Markovich, Jaynal A. Molla
  • Patent number: 5432998
    Abstract: Disclosed is a method of laminating circuitized polymeric dielectric panels with pad to pad electrical connection between the panels. This pad to pad electrical connection is provided by a transient liquid phase formed bond of a joining metallurgy characterized by a non-eutectic stoichiometry composition of a eutectic forming system. The eutectic temperature of the system is below the first thermal transition of the polymeric dielectric, and the melting temperature of the joining metallurgy composition is above the first thermal transition temperature of the polymeric dielectric.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: July 18, 1995
    Assignee: International Business Machines, Corporation
    Inventors: Raymond T. Galasco, Jaynal A. Molla
  • Patent number: 5298685
    Abstract: Polymeric subcomposites of a circuit board are interconnected by metallic dendrites on electrical contact pads whereby electrical contact pads of one or the subcomposites are larger widthwise than electrical contact pads of the other subcomposite.
    Type: Grant
    Filed: July 14, 1992
    Date of Patent: March 29, 1994
    Assignee: International Business Machines Corporation
    Inventors: Perminder S. Bindra, Ross Downey Havens, Voya R. Markovich, Jaynal A. Molla
  • Patent number: 5237743
    Abstract: A method of forming conductive end portions on a flexible circuit member having a dielectric layer (e.g., polyimide) with at least one conductive element (e.g., copper) thereon. The method comprises the steps of forming (e.g., punching) an opening through both dielectric and conductive element, providing (e.g., additive plating) an electrically conducting layer on the opening's internal surface, providing (e.g., electroplating) a plurality of dendritic elements on the conducting layer's surface, and thereafter removing (e.g., punching) a portion of the dielectric and conductive element such that the formed dendritic elements (e.g., palladium) project from the flexible circuit's conductive ends.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: August 24, 1993
    Assignee: International Business Machines Corporation
    Inventors: Raymond A. Busacco, Fletcher W. Chapin, David W. Dranchak, Jaynal A. Molla, George J. Saxenmeyer, Jr., Robert D. Topa
  • Patent number: 5185073
    Abstract: A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. Pulse electroplating of palladium provides a dendritic deposit of uniform height, uniform rounded points and less branching. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: February 9, 1993
    Assignee: International Business Machines Corporation
    Inventors: Perminder S. Bindra, Jerome J. Cuomo, Thomas P. Gall, Anthony P. Ingraham, Sung K. Kang, Jungihl Kim, Paul Lauro, David N. Light, Voya R. Markovich, Ekkehard F. Miersch, Jaynal A. Molla, Douglas O. Powell, John J. Ritsko, George J. Saxenmeyer, Jr., Jack A. Varcoe, George F. Walker
  • Patent number: 5137461
    Abstract: A separable and reconnectable connection for electrical equipment is provided that is suitable for miniaturization in which vertical interdigitating members integrally attached and protruding from a planar portion are accommodated in control of damage in lateral displacement that occurs on mating with an opposite similar contact. Displacement damage is averted through accommodating lateral stresses by providing one or more of a conformal opposing contact, by strengthening through coating and base reinforcement and a deformable coating. The contacts are fabricated by physical and chemical processes including sputtering, normal and pulse electroplating and chemical vapor deposition. The contacts on completion are provided with a surrounding immobilizing material that enhances rigidity.
    Type: Grant
    Filed: October 30, 1990
    Date of Patent: August 11, 1992
    Assignee: International Business Machines Corporation
    Inventors: Perminder S. Bindra, Jerome J. Cuomo, Thomas P. Gall, Anthony P. Ingraham, Sung K. Kang, Jungihl Kim, Paul Lauro, David N. Light, Voya R. Markovich, Ekkehard F. Miersch, Jaynal A. Molla, Douglas O. Powell, John J. Ritsko, George J. Saxenmeyer, Jr., Jack A. Varcoe, George F. Walker
  • Patent number: 4894296
    Abstract: The invention relates to an improved hydrophobic cathode for use in a zinc-air cell, and to a method for making said cathode. The cathode comprises an admixture of discrete particles of gamma manganese dioxide and carbon and a polymeric halogenated hydrocarbon. The method includes the step of intensively milling the manganese dioxide to reduce the particle size thereof and homogeneously admixing the manganese dioxide with the carbon particles.
    Type: Grant
    Filed: October 27, 1987
    Date of Patent: January 16, 1990
    Assignee: Duracell Inc.
    Inventors: Alex Borbely, Jaynal Molla