Patents by Inventor Jaynal A. Molla

Jaynal A. Molla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9589860
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9538659
    Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: January 3, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mahesh K. Shah
  • Publication number: 20160365323
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 15, 2016
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Patent number: 9425161
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20160126206
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20160099199
    Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 7, 2016
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla
  • Publication number: 20150333031
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Application
    Filed: July 24, 2015
    Publication date: November 19, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. MAHALINGAM, DAVID F. ABDO, JAYNAL A. MOLLA
  • Patent number: 9099567
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20150146399
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Publication number: 20150055310
    Abstract: An embodiment of a solder wettable flange includes a flange body formed from a conductive material. The flange body has a bottom surface, a top surface, sidewalls extending between the top surface and the bottom surface, and one or more depressions extending into the flange body from the bottom surface. Each depression is defined by a depression surface that may or may not be solder wettable. During solder attachment of the flange to a substrate, the depressions may function as reservoirs for excess solder. Embodiments also include devices and systems that include such solder wettable flanges, and methods for forming the solder wettable flanges, devices, and systems.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Inventors: LAKSHMINARAYAN VISWANATHAN, Jaynal A. Molla, Mahesh K. Shah
  • Patent number: 7829980
    Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: November 9, 2010
    Assignee: Everspin Technologies, Inc.
    Inventors: Jaynal A. Molla, Eric J. Salter
  • Patent number: 7598596
    Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 6, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, Gregory W. Grynkewich, Eric J. Salter
  • Publication number: 20080266938
    Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.
    Type: Application
    Filed: April 24, 2007
    Publication date: October 30, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, Eric J. Salter
  • Patent number: 7402529
    Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
  • Publication number: 20080116535
    Abstract: A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventors: Jaynal A. Molla, Gregory W. Grynkewich, Eric J. Salter
  • Patent number: 7279341
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: May 9, 2005
    Date of Patent: October 9, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam
  • Patent number: 7105363
    Abstract: A method for fabricating a cladded conductor (42) for use in a magnetoelectronics device is provided. The method includes providing a substrate (10) and forming a conductive barrier layer (12) overlying the substrate (10). A dielectric layer (16) is formed overlying the conductive barrier layer (12) and a conducting line (20) is formed within a portion of the dielectric layer (16). The dielectric layer (16) is removed and a flux concentrator (30) is formed overlying the conducting line (20).
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 12, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Mark A. Durlam, Jeffrey H. Baker, Brian R. Butcher, Mark F. Deherrera, John J. D'Urso, Earl D. Fuchs, Gregory W. Grynkewich, Kelly W. Kyler, Jaynal A. Molla, J. Jack Ren, Nicholas D. Rizzo
  • Publication number: 20050263400
    Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 1, 2005
    Inventors: Jaynal Molla, John D'Urso, Kelly Kyler, Bradley Engel, Gregory Grynkewich, Nicholas Rizzo
  • Publication number: 20050208681
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Application
    Filed: May 9, 2005
    Publication date: September 22, 2005
    Inventors: Thomas Meixner, Gregory Grynkewich, Jaynal Molla, J. Ren, Richard Williams, Brian Butcher, Mark Durlam
  • Patent number: 6943038
    Abstract: A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 13, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas V. Meixner, Gregory W. Grynkewich, Jaynal A. Molla, J. Jack Ren, Richard G. Williams, Brian R. Butcher, Mark A. Durlam