Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.

Abstract: A semiconductor device having a recessed landing pad includes a semiconductor substrate and a lower interlayer dielectric layer disposed on the semiconductor substrate. A first landing pad is disposed through the lower interlayer dielectric layer to be in contact with the semiconductor substrate. A second landing pad is disposed through the lower interlayer dielectric layer to also be in contact with the semiconductor substrate. A metal silicide layer is disposed on the second landing pad. The metal silicide layer is disposed lower than a top surface of the first landing pad. An intermediate interlayer dielectric layer is disposed on the lower interlayer dielectric layer. A conductive line is disposed on the intermediate interlayer dielectric layer. A contact plug is disposed between the conductive line and the metal silicide layer. A designed contact area between the metal silicide layer and the contact plug is protected against inadvertent etching.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: A contact structure having silicide layers, a semiconductor device employing the same, and methods of fabricating the contact structure and semiconductor device are provided. The contact structure includes a first conductive region and a second conductive region on a substrate. An insulating layer covers the first and second conductive regions. A first contact hole and a second contact hole are formed through the insulating layer and expose the first and second conductive regions, respectively. A first silicide layer having a first thickness is on the first conductive region exposed by the first contact hole. A second silicide layer having a second thickness different than the first thickness is on the second conductive region exposed by the second contact hole.

Abstract: A semiconductor device including square type storage nodes and a method of manufacturing the same. Word lines are formed on a semiconductor substrate Bit lines are formed separated from the word lines and perpendicular to the word lines. Active regions are defined to have a major axis slanted to the word line direction and the bit line direction. Storage nodes of capacitors are arranged along the word lines overlapping the word lines and arranged in a zigzag pattern that centers upon the bit lines. Storage node contacts are formed to electrically connect the active regions to the storage nodes, while being self-aligned with the bit lines, separated from each other on the word lines, and with a larger line width in the word line direction than the bit line direction to overlap large areas of the storage nodes.

Abstract: A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.

Abstract: In one embodiment, a semiconductor device includes a plurality of gate electrodes formed on a semiconductor substrate including a cell region, a core region, and a peripheral circuit region, along with source/drain regions. A first landing pad contacts the source/drain of the cell region. A second landing pad contacts the source/drain of an NMOS of the core region. A First, second, third, and fourth contact plug, each surrounded by spacers, respectively contact the first landing pad, the second landing pad, the source/drain of a PMOS of the core region, and the source/drain of the peripheral circuit region. Also, a fifth and sixth contact plug, respectively contact the source/drain of the NMOS of the peripheral circuit region and the gate conductive layer included in the gate electrode of the peripheral circuit region.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: A semiconductor device comprises a semiconductor substrate including an isolation region defining an active area with a plurality of source/drain regions. A contact pad layer is formed on the semiconductor substrate and includes gate line structures, first contact pads connected to parts of the source/drain regions, second contact pads connected to the other source/drain regions. A first interlevel dielectric layer covers the gate line structures and the first and second contact pads. A bit line contact plug layer is formed on the contact pad layer and includes lower storage node contact plugs connected to the first contact pads, bit line contact plugs connected to the second contact pads. A protective layer pattern is formed on the second contact pads to prevent the second contact pads from being connected to the lower storage node contact plugs and/or upper storage node contact plugs.

Abstract: A semiconductor device having a contact includes a semiconductor substrate having a core region, a first interlayer insulating layer disposed on the semiconductor substrate, a first interconnect line disposed on the first interlayer insulating layer, the first interconnect line extending in a first direction, and a conductive stud covering a sidewall of the first interconnect line, the conductive stud penetrating the first interlayer insulating layer to contact the semiconductor substrate.

Abstract: A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage electrode and an adjacent storage electrode, all of the storage electrodes in a unit cell of a semiconductor device are structured to prevent a collapse. Also, the semdevice can have a very high height without collapse when the capacitors have extremely high aspect ratios. Therefore, the capacitors may have greatly enhanced capacitance in comparison with a conventional capacitor.

Abstract: In a method of manufacturing a semiconductor device including a capacitor having improved structural stability and enhanced capacitance, a contact region is formed on a surface portion of a semiconductor substrate. After a mold layer is formed on the substrate, a stabilizing member is formed to encompass a storage electrode. A contact hole is formed through the mold layer to expose a sidewall of the stabilizing member and the contact region. The storage electrode is formed on the exposed contact region and on the exposed sidewall of the stabilizing member. A dielectric layer and a plate electrode are successively formed on the storage electrode. The capacitor including the storage electrode and the stabilizing member will have improved structural stability that resists mechanical collapse even when the capacitor has an extremely high aspect ratio.

Abstract: A method includes preparing a semiconductor substrate having a cell region, a core NMOS region, and a core PMOS region; defining a cell active region, an NMOS active region, and a PMOS active region in the cell region, the core NMOS region, and the core PMOS region, respectively, by forming an isolation layer in predetermined regions of the semiconductor substrate; forming a cell gate pattern, an NMOS gate pattern, and a PMOS gate pattern crossing the cell active region, the NMOS active region, and the PMOS active region, respectively; forming an interlayer-insulating layer on the semiconductor substrate having the gate patterns; simultaneously forming a storage node landing pad, a bit line landing pad, and NMOS landing pads; and patterning the interlayer-insulating layer of the core PMOS region to form PMOS interconnection contact holes that expose predetermined regions of the PMOS active region adjacent to the PMOS gate pattern.

Abstract: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

Abstract: In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

Abstract: A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage electrode and an adjacent storage electrode, all of the storage electrodes in a unit cell of a semiconductor device are structured to prevent a collapse. Also, the semdevice can have a very high height without collapse when the capacitors have extremely high aspect ratios. Therefore, the capacitors may have greatly enhanced capacitance in comparison with a conventional capacitor.

Abstract: A storage node contact forming method and structure reduces the number of processes required by the conventional art and increases a critical dimension of a storage node to prevent a leaning phenomenon and reduce a manufacturing cost of semiconductor memory devices. The method includes preparing a semiconductor substrate that involves at least one contact pad contacted with an active region of a memory cell transistor through an insulation layer. The method also includes forming a storage node contact of T-shape, the storage node contact being composed of a lower region contacted with an upper part of the contact pad, and an upper region that is extended to a gate length direction of the memory cell transistor and that is formed as a size larger than a size of the lower region, in order to electrically connect the contact pad with a storage node to be formed in a later process.

Abstract: In one embodiment, an etch stop layer and a mold layer is sequentially formed on a semiconductor substrate having an interlayer insulation layer. The interlayer insulation layer includes a conductive region formed therein. The mold layer is partially etched to expose a top surface of the etching stop layer. The exposed etching stop layer and an upper portion of the interlayer insulating layer are removed to form a first aperture part that exposes a portion of the conductive region. The conductive region exposed in the first aperture part is etched to form a second aperture part. A conductive layer for the capacitor storage node is deposited on the semiconductor substrate having the first and second aperture parts. The conductive layer provided on the mold layer is planarized to form separated capacitor storage nodes.

Abstract: A semiconductor memory device comprises a cell capacitor having a first buried contact connected with a semiconductor substrate of a cell region and a first storage node connected with the first buried contact, and a decoupling capacitor for reducing a coupling noise, having a plurality of second buried contacts formed on a semiconductor substrate portion adjacent in the cell region and extended in parallel with each other and a plurality of second storage nodes connected with the second buried contacts.

Abstract: A semiconductor device comprises a semiconductor substrate and an interlayer insulating layer formed on the semiconductor substrate. The interlayer insulating layer preferably has a contact pad formed therein. A capacitor lower electrode is electrically connected to the contact pad. The capacitor lower electrode further comprises a pad-shaped storage node electrically connected to the contact pad; and a cup-shaped storage node arranged on the pad-shaped storage node. In this manner, it is possible to increase capacitance while reducing not open contacts. Leaning of the storage nodes can also be significantly reduced.