Abstract: A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.

Abstract: A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

Abstract: Integrated circuit capacitor electrodes include a first conductive ring on a face of an integrated circuit substrate. A second conductive ring is provided on the first conductive ring opposite the substrate. A third conductive ring also is provided on the first conductive ring opposite the substrate. The third ring is located at least partially within the second ring. A conductive layer electrically connects the first, second and third rings. To form the electrodes, a first conductive layer is conformally deposited in the areas in which the electrodes will be formed and on a mold oxide layer. A first buffer dielectric layer is deposited on the first conductive layer. The first buffer dielectric layer and the first conductive layer are etched to separate nodes of the first conductive layer. Recessed portions are formed by further etching the first conductive layer.

Abstract: The present invention provides a semiconductor device having a spacer pattern and methods of forming the same that includes a lower interconnection pattern on a semiconductor substrate. A lower interconnection spacer covers sidewalls of the lower interconnection pattern. Spacer patterns cover the lower interconnection spacer of the lower interconnection pattern and disposed on the semiconductor substrate. An upper interconnection pattern is formed between the spacer patterns.

Abstract: In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer insulating layer pattern over the BC pads. The exposed sidewall of the interlayer insulating layer pattern is covered with an etch stop spacer. Also, the top surface of the interlayer insulating layer pattern is covered with an etch stop layer. Then, a plurality of bit line contact or BC plugs are formed to contact the tops of the BC pads. A protruded region, which extends in one direction, is preferably formed on the sidewall of the contact plug.

Abstract: The present invention discloses a semiconductor device, comprising: bit line landing pads formed over a semiconductor substrate; storage landing pads formed on both sides of the bit line landing pads; a bit line interlayer insulator formed over the whole surface of the semiconductor substrate having the landing pads; a plurality of parallel bit line patterns arranged on the bit line interlayer insulator; bit line insulating layer patterns filling in gate regions between the bit line patterns; upper contact holes formed in the bit line insulating layer patterns to expose side walls of the bit line patterns and located higher than upper surfaces of the bit line patterns; contact hole spacers covering the side walls of the upper contact holes; lower contact holes penetrating the bit line insulating layer patterns and the bit line interlayer insulator below holes surrounded by the contact hole spacers to expose the storage node landing pads and self-alighed with the upper contact holes; and storage node contact p

Abstract: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction where the adjacent storage electrode is arranged. A dielectric layer is formed on the storage electrode. A plate electrode is formed on the dielectric layer.

Abstract: In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer insulating layer pattern over the BC pads. The exposed sidewall of the interlayer insulating layer pattern is covered with an etch stop spacer. Also, the top surface of the interlayer insulating layer pattern is covered with an etch stop layer. Then, a plurality of bit line contact or BC plugs are formed to contact the tops of the BC pads. A protruded region, which extends in one direction, is preferably formed on the sidewall of the contact plug.

Abstract: A semiconductor substrate has a cell region and a peripheral circuit region surrounding the cell region. In the cell region a plurality of lower electrodes are connected to a conductive region of the semiconductor substrate, and are arrayed along row and column directions. A dielectric layer is formed on the plurality of lower electrodes. An upper electrode is formed on the dielectric layer, entirely covering the cell region, and is formed extending to a portion of the peripheral circuit region that has a step coverage lower by a height of the lower electrode than the cell region. An edge of the upper electrode has square-shaped projections that are distanced from each other at a uniform interval and are repetitively arrayed. With the described structure, pattern defects can be sensed and controlled, preventing and substantially reducing process defect.

Abstract: A semiconductor device including square type storage nodes and a method of manufacturing the same. Word lines are formed on a semiconductor substrate Bit lines are formed separated from the word lines and perpendicular to the word lines. Active regions are defined to have a major axis slanted to the word line direction and the bit line direction. Storage nodes of capacitors are arranged along the word lines overlapping the word lines and arranged in a zigzag pattern that centers upon the bit lines. Storage node contacts are formed to electrically connect the active regions to the storage nodes, while being self-aligned with the bit lines, separated from each other on the word lines, and with a larger line width in the word line direction than the bit line direction to overlap large areas of the storage nodes.

Abstract: A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.

Abstract: A method of manufacturing a semiconductor device with contact bodies that extend in the direction of bit lines to contact storage nodes includes forming band-type openings by selectively etching an insulating layer that covers the bit lines. The band-type openings extend in a lengthwise direction of the gate lines to expose the first contact pads and have portions that protrude in a lengthwise direction of the bit lines. The method also includes forming a conductive layer on the insulating layer that fills the band-type openings and is electrically connected to the first contact pads. The conductive layer is then patterned to separate the conductive layer into individual storage node contact bodies that extend in a lengthwise direction of the bit lines. Storgage nodes are then formed on the storage node contact bodies.

Abstract: A second insulating layer is formed on a first insulating layer. A plurality of stacks each including a bit line and a bit line mask are formed on the second insulating layer. A third insulating layer is formed overlying the second insulating layer to fill gaps between the plurality of stacks. A hard mask layer is formed on the third insulating layer. A photoresist pattern is formed on the hard mask layer. The photoresist pattern has an opening region that intersects the plurality of stacks. The hard mask layer and the third insulating layer are sequentially etched, using the photoresist pattern as an etching mask, thereby forming a hard mask pattern and forming a recess in the third insulating layer. The recess exposes a portion of upper sidewalls of the bit line mask. Spacers are formed on the exposed upper sidewalls of the bit line mask.

Abstract: A semiconductor device has a stabilizing member that encloses an upper portion of a storage electrode to improve structural stability. A dielectric layer and a plate electrode are successively formed on the storage electrode including a stabilizing member. Since the stabilizing member includes a protruding portion to support the storage electrode and an adjacent storage electrode, all of the storage electrodes in a unit cell of a semiconductor device are structured to prevent a collapse. Also, the semdevice can have a very high height without collapse when the capacitors have extremely high aspect ratios. Therefore, the capacitors may have greatly enhanced capacitance in comparison with a conventional capacitor.

Abstract: In one embodiment, a plurality of contact holes are formed using an self-aligned contact (SAC) process to expose active regions. When storage node contact or BC pads are formed in the contact holes, a conductive layer is partially filled in the contact holes to expose the sidewall of an interlayer insulating layer pattern over the BC pads. The exposed sidewall of the interlayer insulating layer pattern is covered with an etch stop spacer. Also, the top surface of the interlayer insulating layer pattern is covered with an etch stop layer. Then, a plurality of bit line contact or BC plugs are formed to contact the tops of the BC pads. A protruded region, which extends in one direction, is preferably formed on the sidewall of the contact plug.

Abstract: A method of fabricating a semiconductor memory device and a structure that forms both a resistor and an etching protection layer to reduce a contact resistance. The method of fabricating a semiconductor memory device according to the invention includes forming an insulation layer on a semiconductor substrate having a cell array region, a core region, and a peripheral region, each having at least one transistor formed therein, and forming both a first landing pad in the core region on the insulation layer and a second landing pad in the peripheral region, the first landing pad being overlapped with a part of a first conductive line. The invention reduces the contact resistance and prevents or minimizes a device failure caused by a misalignment, with the simplified process.

Abstract: According to some embodiments, a capacitor includes a storage conductive pattern, a storage electrode having a complementary member enclosing a storage conductive pattern so as to complement an etch loss of the storage electrode, a dielectric layer disposed on the storage electrode, and a plate electrode disposed on the dielectric layer. Because the complementary member compensates for the etch loss of the storage electrode during several etching processes, the deterioration of the structural stability of the storage electrode may be prevented. Additionally, because the complementary member is formed on an upper portion of the storage electrode, the storage electrode may have a sufficient thickness to enhance the electrical characteristics of the capacitor that includes the storage electrode.

Abstract: A method for fabricating a semiconductor device, in which a sufficient misalignment margin is obtained when forming interconnections and contact holes, is provided. Dielectric layer patterns which define recesses in which damascene interconnections are to be formed, are formed. Then, first contact holes between the dielectric layer patterns are etched, and the first contact holes and the recesses are concurrently filled with a conductive material. The recesses can be filled with the conductive material by performing an etch-back process. The dielectric layer patterns are then etched, thereby forming the damascene interconnections and concurrently covering only a region in which second contact holes are to be formed with the dielectric layer patterns. Spaces between the dielectric layer patterns are filled with a mask layer, and then the dielectric layer patterns are selectively removed from the resultant structure, thereby forming the second contact holes aligned with the damascene interconnections.

Abstract: In a semiconductor device according to embodiments of the invention, a capacitor includes a storage electrode having a cylindrical storage conductive layer pattern and connecting members formed on the upper portion of the cylindrical storage conductive layer pattern. The connecting member connects to an adjacent connecting member of another storage electrode. A dielectric layer and a plate electrode are successively formed on the storage electrode. All of the capacitors are connected by one another by forming cylindrical storage electrodes so that the storage electrode does not fall down when the capacitors have an extremely large aspect ratio. Thus, the capacitance of the capacitors may be improved to the desired level. A semiconductor device that includes these capacitors may have improved reliability and the throughput of a semiconductor manufacturing process may be increased.

Abstract: A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.