Patents by Inventor Jean-Jacques Lecler
Jean-Jacques Lecler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11520706Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.Type: GrantFiled: April 29, 2021Date of Patent: December 6, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Rakesh Kumar Gupta, Subbarao Palacharla, Kedar Bhole, Laurent Rene Moll, Carlo Spitale, Sparsh Singhai, Shyamkumar Thoziyoor, Gopi Tummala, Christophe Avoinne, Samir Ginde, Syed Minhaj Hassan, Jean-Jacques Lecler, Luigi Vinci
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Publication number: 20220350749Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.Type: ApplicationFiled: April 29, 2021Publication date: November 3, 2022Inventors: Alain ARTIERI, Rakesh Kumar GUPTA, Subbarao PALACHARLA, Kedar BHOLE, Laurent Rene MOLL, Carlo SPITALE, Sparsh SINGHAI, Shyamkumar THOZIYOOR, Gopi TUMMALA, Christophe AVOINNE, Samir GINDE, Syed Minhaj HASSAN, Jean-Jacques LECLER, Luigi VINCI
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Patent number: 11403217Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.Type: GrantFiled: March 18, 2020Date of Patent: August 2, 2022Assignee: QUALCOMM IncorporatedInventors: Alain Artieri, Jean-Jacques Lecler, Shyamkumar Thoziyoor
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Publication number: 20220019459Abstract: Aspects of the present disclosure provide techniques for controlling early responses in systems employing master devices and slave devices. An example method for controlling a slave device includes receiving a plurality of transaction requests from a master device for the slave device to execute and respond, determining whether a response criterion is met based on a number of the plurality of transaction requests that have been executed and a number of response messages transmitted to the master device for the plurality of transaction requests, while the response criterion is met, proceeding with transmitting response messages for the plurality of transaction requests, and while the response criterion is not met, refraining from transmitting response messages for any of the plurality of transaction requests.Type: ApplicationFiled: July 20, 2020Publication date: January 20, 2022Inventor: Jean-Jacques LECLER
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Publication number: 20210382651Abstract: In some aspects, the present disclosure provides a method for scheduling transactions for a memory by a scheduler. The method includes receiving a plurality of transactions, each of the plurality of transactions being associated with a corresponding priority level. The method also includes selecting one or more transactions of the plurality of transactions that meet one or more constraints based on one or more past transactions scheduled for the memory by the scheduler. The method also includes determining whether at least one transaction of the one or more transactions satisfies a threshold priority level.Type: ApplicationFiled: June 5, 2020Publication date: December 9, 2021Inventors: Jean-Jacques LECLER, Philippe BOUCARD
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Patent number: 11126431Abstract: A method for dynamic memory scheduling with enhanced bank-group batching is described. The method includes determining a read-bank group-spread of each rank, as a number of bank-groups of each respective rank targeted by at least one read instruction. The method further includes determining a write-bank group-spread of each rank, as a number of bank-groups of each rank targeted by at least one write instruction. The method also includes stalling a current batch of read instructions in a rank when the read-bank group-spread of the rank is less than a predetermined value. The method further includes stalling a current batch of write instructions in a rank when the write-bank group-spread of the rank is less than the predetermined value.Type: GrantFiled: May 29, 2020Date of Patent: September 21, 2021Assignee: QUALCOMM IncorporatedInventors: Jean-Jacques Lecler, Alain Artieri
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Publication number: 20210133100Abstract: Memory utilization in an SDRAM system may be improved by increasing memory bank group and memory bank interleaving. Memory bank group interleaving and memory bank interleaving may be increased by a memory controller generating a physical memory address in which the bank group address bits are positioned nearer the LSB of the physical memory address than the MSB. Alternatively, or in addition to positioning the bank group address bits in such a manner, memory bank group interleaving and memory bank interleaving may be increased by hashing the bank group address bits and bank address bits of the physical memory address with row address bits of the initial physical memory address, A rank address bit may also be involved in the hashing.Type: ApplicationFiled: March 18, 2020Publication date: May 6, 2021Inventors: Alain ARTIERI, Jean-Jacques LECLER, Shyamkumar THOZIYOOR
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Patent number: 10951230Abstract: In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.Type: GrantFiled: March 17, 2020Date of Patent: March 16, 2021Assignee: Qualcomm IncorporatedInventors: Jean-Jacques Lecler, Christophe Jean-Luc Layer
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Patent number: 9882839Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.Type: GrantFiled: May 25, 2015Date of Patent: January 30, 2018Assignee: QUALCOMM IncorporatedInventors: Philippe Boucard, Jean-Jacques Lecler
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Patent number: 9639469Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.Type: GrantFiled: July 13, 2013Date of Patent: May 2, 2017Assignee: Qualcomm Technologies, Inc.Inventors: Laurent Moll, Jean-Jacques Lecler, Jonah Proujansky-Bell
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Patent number: 9563560Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.Type: GrantFiled: July 10, 2013Date of Patent: February 7, 2017Assignee: Qualcomm Technologies, Inc.Inventors: Laurent Moll, Jean-Jacques Lecler
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Patent number: 9503222Abstract: A first frame and a second frame are combined into an extended frame. The extended frame is encapsulated and transmitted over a channel as an extended physical digital. A transmission error notification is received, indicating error in a reception of the transmitted extended physical digital. In response, a re-transmission encapsulates the first frame into a first physical digit, transmits the first physical digit over the channel, encapsulates the second frame into a second physical digit, and transmits the second physical digit over the channel.Type: GrantFiled: December 7, 2012Date of Patent: November 22, 2016Assignee: Qualcomm Technologies, Inc.Inventors: Philippe Martin, Jonah Probell, Jean-Jacques Lecler
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Patent number: 9471538Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.Type: GrantFiled: September 25, 2012Date of Patent: October 18, 2016Assignee: Qualcomm Technologies, Inc.Inventors: Philippe Boucard, Jean-Jacques Lecler, Boris Boutillier
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Patent number: 9465749Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.Type: GrantFiled: August 17, 2013Date of Patent: October 11, 2016Assignee: Qualcomm Technologies, Inc.Inventors: Laurent Moll, Jean-Jacques Lecler, Philippe Boucard
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Patent number: 9396130Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.Type: GrantFiled: August 16, 2013Date of Patent: July 19, 2016Assignee: Qualcomm Technologies, Inc.Inventors: Philippe Boucard, Jean-Jacques LeCler, Laurent Moll
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Patent number: 9361230Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.Type: GrantFiled: September 20, 2015Date of Patent: June 7, 2016Assignee: Qualcomm Technologies, Inc.Inventor: Jean-Jacques Lecler
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Patent number: 9280468Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.Type: GrantFiled: October 24, 2012Date of Patent: March 8, 2016Assignee: Qualcomm Technologies, Inc.Inventor: Jean-Jacques Lecler
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Publication number: 20160011976Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.Type: ApplicationFiled: September 20, 2015Publication date: January 14, 2016Inventor: Jean-Jacques LECLER
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Patent number: 9225665Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.Type: GrantFiled: September 25, 2012Date of Patent: December 29, 2015Assignee: QUALCOMM TECHNOLOGIES, INC.Inventors: Philippe Boucard, Jean-Jacques Lecler, Boris Boutillier
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Patent number: 9141556Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.Type: GrantFiled: August 16, 2013Date of Patent: September 22, 2015Assignee: Qualcomm Technologies, Inc.Inventors: Laurent Moll, Jean-Jacques LeCler, Philippe Boucard