Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

Abstract: The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

Abstract: A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.

Abstract: Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.

Abstract: Verification IPs for the verification of semiconductor chip designs are designed to support specific interface protocols. Verification IP is expensive or unavailable to test devices with interfaces of uncommon protocols. Verification IP that uses a generic interface protocol, used in conjunction with simple adapters between interfaces of the VIP that use the generic protocol and interfaces of the device under test that use specific protocols, are reused to test interfaces with different specific protocols if the generic protocol supports a superset of the features of the specific protocols.

Abstract: The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages.

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract: A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store.

Abstract: A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput.

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract: The invention is a transaction interface protocol wherein the interface protocol has a transaction identifier signal in each of the request and response channels. It is used between a target network interface unit (NIU) master and an initiator NIU slave that are directly connected through a transaction interface. The target NIU response channel uses the transaction ID signal to identify the entry in a context array associated with the corresponding request. The coupling of target NIU and initiator NIU enable the formation of an on-chip interconnect comprising multiple network-on-chip (NoCs) wherein the topology of the interconnect is simpler, smaller, faster, and has lower latency.

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract: A system TLB accepts translation prefetch requests from initiators. Misses generate external translation requests to a walker port. Attributes of the request such as ID, address, and class, as well as the state of the TLB affect the allocation policy of translations within multiple levels of translation tables. Translation tables are implemented with SRAM, and organized in groups.

Abstract: A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.

Abstract: A system and method are disclosed for connecting PCI-ordered agents based on fully independent networks. The system and method are free of PCI topology constraints, so that the system and method can be implemented in an inexpensive and scalable way. The method disclosed is used to handle and transport PCI-ordered traffic on a fabric. Based on the actual ordering requirement of the set of PCI agents, the fabric includes two, three, or four independent networks.