Abstract: A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

Abstract: A storage circuit using a dual-access memory, comprising means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access, at least two successive activations of said means controlling operations of the same type, reading or writing.

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract: An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.

Abstract: An integrated circuit comprising a semiconductor substrate in which active areas surround or are surrounded by hollowings filled with an insulator, and in which a conductive region is embedded in the insulator of at least one hollowing, the conductive region being connected to a reference voltage and being connected at least one neighboring element of the circuit.

Abstract: A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.

Abstract: A method for adapting to specific needs an integrated circuit having a stack of insulating layers, each layer being associated with a determined metallization level, metal areas of the last metallization level forming electric contacts of the integrated circuit, including the steps of forming pairs of metal regions of the penultimate metallization level having a facing edge and connected to components of the integrated circuit; depositing an insulating layer; etching according to the specific needs the insulating layer to expose the facing edges of the metal regions of determined pairs; and forming metal portions of the last metallization level which cover the facing edges of the metal regions of all pairs and which contact the metal regions of the determined pairs.

Abstract: A memory circuit with an error correcting system comprising an address bus (102), an input data bus (108), and an output data bus (115), the circuit comprising a memory having an address bus (113), a data bus (114) and an error correcting circuit comprising an encoder (107). A first address register (104) is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register (105) is connected to the input data bus of the circuit (108) for storing data transmitted to the encoder (107). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract: A component of an integrated circuit comprises a first capacitor and a second capacitor series-connected between a first node and a second node of the component. This has application to logic circuits and bistable circuits, for example, SRAM type memories, flip-flop trigger circuits, etc.

Abstract: An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Abstract: The present invention relates to a logic simulation method, in which a signal is switched between two logic states to simulate a transition of a real signal. The method comprises the step of inserting between the two logic states of the signal an intermediate state for a time interval indicative of the slope of the transition of the real signal.

Abstract: An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Abstract: A circuit for checking the parity of the contents of a register is provided. The register has a test mode in which a scan input of each flip-flop in the register is connected to a scan output of a preceding flip-flop to form a scan path. The parity checking circuit includes an XOR gate for at least each flip-flop from the second flip-flop to the last flip-flop of the register. Each XOR gate has one input connected to the normal output of the associated flip-flop, another input connected to the scan input for the flip-flop, and an output connected to the scan output of the flip-flop when not in the test mode. The result of the parity checking operation is generated at the output of the XOR gate associated with the last flip-flop of the register. In preferred embodiments, for each flip-flop of the register, the normal output of the flip-flop is supplied to the scan output in the test mode, and the output of the associated XOR gate is supplied to the scan output when not in the test mode.

Abstract: An OTP memory cell in CMOS technology, including a capacitor associated in series with an unbalanced programming transistor, the drain of which is made of a region deeper and less doped than the source.

Abstract: The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Abstract: A read only memory integrated semiconductor device includes at least one memory cell. The memory cell includes a storage transistor made within a semiconductor substrate and whose source is connected to ground. A word line is connected to the gate of the transistor. Only one of several bit lines may be connected to the drain of the transistor at a time.