Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Abstract: A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, each having a selection input, first and second data inputs, and an output. Each of the plurality of logic cells has a first input and an output, the output of each logic cell in the series being respectively electrically coupled to the first input of a next logic cell in the series. The output of a last logic cell in the series is electrically coupled to the first input of a first logic cell in the series to form a ring. The selection input of each multiplexer of the plurality of multiplexers is electrically coupled to the output of one logic cell in the series, with the output of each multiplexer being electrically coupled to the first input of the next logic cell in the series.

Abstract: A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Abstract: A programmable non-volatile memory device has a plurality of rows of memory cells that are accessible through selection addresses, with the number of physical rows being greater than the number of rows that are addressable at a given time. An associating circuit associates selected physical rows of the memory device with selection addresses. The associating circuit includes an associative memory that has a programmable memory location for each physical row of the memory device, and each memory location in the associative memory has an address field and at least one state bit. In one preferred embodiment, in the read mode, a row of the memory device is selected when the corresponding memory location in the associative memory contains the received address and state bits indicating that the row stores valid data for the received address. A method of programming such a non-volatile memory device is also provided.

Abstract: The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.

Abstract: A circuit, indicating the first or last signal activated among n signals, includes flip-flops respectively associated with pairs of signals, a first signal of each pair being applied to a reset input of a flip-flop and a second signal of each pair being applied to a set input. Logic gates are respectively associated with each considered signal and are connected to indicate whether the considered signal is the first or the last activated signal when the flip-flops associated with all the pairs of signals including the considered signal are at respective suitable states once the first or last signal is activated.

Abstract: A device checks the skew between two clock signals among a plurality of clock signals having the same frequency. The two clock signals of each possible pair of clock signals respectively enable two successive flip-flops that are initially set at distinct states. The whole set of the flip-flops is connected in a looped shift register configuration. An alarm signal is provided by an Exclusive-OR gate receiving the outputs of two successive flip-flops of the shift register.

Abstract: A bus control device for a central processing unit (CPU) comprising a plurality of isolatable segments, which permits the transfer of data from one segment to another two adjacent segments being connected with one another via switches (S01, S11, S02, S12) controlled by a selection signal (C12, C23), an amplification device (A1, A2, A3) controlled by an actuation signal (CA1, CA2, CA3) being associated with each bus segment for amplifying the voltages that appear on the lines (B01, B11, B02, B12, B03, B13) of this segment, said control device being characterized in that it includes slaving means (12, 13, 16, 22, 23, 26) for actuating the amplifier of any one segment is response to the actuation of the amplifier of a segment adjacent to the this segment and in reponse to the selection signal (C12, C23) for the switches that connect this segment to said adjacent segment.