Patents by Inventor Jeen PARK

Jeen PARK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220012033
    Abstract: A controller that controls a memory device, includes: a buffer memory; and a processor suitable for: temporarily storing bridge firmware data in the buffer memory when the bridge firmware data is received together with a previous firmware update request, installing and executing bridge firmware based on the bridge firmware data after approved retention firmware data is received together with a subsequent firmware update request, installing the approved retention firmware after execution of the bridge firmware, and removing the installed bridge firmware.
    Type: Application
    Filed: January 14, 2021
    Publication date: January 13, 2022
    Inventor: Jeen PARK
  • Patent number: 11216380
    Abstract: Provided is an operation method of a controller which controls a memory device. The operation method may include: determining a caching order of plural pieces of map data included in a request map segment including request map data; requesting the request map segment from the memory device; marking data in a marking region which is determined based on the caching order; caching, in the caching order, the plural pieces of map data read from the memory device; and acquiring the request map data from the cached data, depending on whether the data stored in the marking region is changed.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Publication number: 20210405888
    Abstract: A memory system includes a memory device including plural non-volatile memory blocks and a controller configured to determine whether a first memory block among the plural non-volatile memory blocks is re-usable after the first memory block is determined to be a bad block and copy second block information associated with a second memory block including a second program sequence number within a set range of a first program sequence number in the first memory block to first block information of the first memory block.
    Type: Application
    Filed: January 8, 2021
    Publication date: December 30, 2021
    Inventor: Jeen PARK
  • Publication number: 20210373797
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 2, 2021
    Inventor: Jeen PARK
  • Patent number: 11188485
    Abstract: A memory system includes a first memory comprising at least one first code region; a second memory comprising at least one second code region; and a control unit configured to perform a first operation by executing a first code loaded to the first code region, and perform a second operation by executing a second code loaded to the second code region. The control unit performs a swap operation on the first code and the second code, based on a swap condition.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Publication number: 20210333999
    Abstract: A data storage device includes: a storage including a plurality of memory blocks; and a controller configured to control a data input/output operation on the storage according to a request from a host device, configure one or more block groups by grouping a preset number of memory blocks among the plurality of memory blocks, configure, as a short block group, a first block group having a first bad block, among the block groups, generate a bit map table based on the position of the first bad block within the short block group, and write data having a preset property to the short block group based on the bit map table.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventor: Jeen PARK
  • Publication number: 20210311825
    Abstract: A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.
    Type: Application
    Filed: September 21, 2020
    Publication date: October 7, 2021
    Inventor: Jeen PARK
  • Patent number: 11137942
    Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The embodiments receive a plurality of requests for a memory device, determine the number of hit requests and the number of miss requests with respect to the plurality of received requests, and determine whether or not to perform all or some of map data read operations for the respective miss requests in parallel and whether or not to perform all or some of user data read operations for the respective hit requests in parallel, thereby minimizing the time required for processing the plurality of requests.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11106581
    Abstract: There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11101017
    Abstract: A memory system includes a memory device including a test region; and a processor configured to write pattern data transferred from a host device to a pattern data region included in the test region, read test data from the test region, and transmit the read test data to the host device. A position of the pattern data region may be adjustable in the test region.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Publication number: 20210255809
    Abstract: A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode.
    Type: Application
    Filed: April 20, 2021
    Publication date: August 19, 2021
    Inventors: Jeen PARK, Jong Min LEE
  • Publication number: 20210241804
    Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventor: Jeen PARK
  • Publication number: 20210224204
    Abstract: A memory system includes a plurality of memory dies and a controller coupled with the plurality of memory dies via a plurality of channels. The controller is configured to perform a correlation operation on at least some read requests among a plurality of read requests inputted from an external device so that the plurality of memory dies outputs plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way. The controller is configured to determine when to perform the correlation operation based on the number of the plurality of read requests.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Inventor: Jeen PARK
  • Patent number: 11055007
    Abstract: A data storage device may include: a storage configured as a group of a plurality of memory blocks; and a controller configured to: control data input/output of the storage according to a request transferred from a host device; configure one or more first block groups by grouping a preset number of memory blocks which are selected at the same time among the memory blocks during an operation of the storage; configure one or more second block groups by replacing a bad memory block of the respective first block groups with a spare memory block; manage as a special block group a second block group where the spare memory block having replaced the bad memory block is not present in the same plane of the bad memory block, among the second block groups; and write data having a preset property to the special block group.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Publication number: 20210200443
    Abstract: A memory system may include a plurality of memory dies configured to store data therein, and a controller coupled to the plurality of memory dies through a plurality of channels, and configured to correlate at least some of a plurality of read requests and transferring the plurality of read requests to the plurality of channels, such that the plurality of read requests are processed in an interleaving way through the plurality of channels, when controlling the plurality of memory dies for the plurality of read requests. The controller may determine whether to perform the correlation operation in response to the number of the plurality of read requests, wherein the plurality of read requests include a read request for an internal operation of the controller and a read request received from a host.
    Type: Application
    Filed: July 2, 2020
    Publication date: July 1, 2021
    Inventor: Jeen PARK
  • Publication number: 20210200444
    Abstract: Disclosed is a memory system including a plurality of memory dies configured to store data in various storage modes; and a controller coupled with the plurality of memory dies via a plurality of channels and configured to perform a correlation operation on multiple read requests among a plurality of read requests received from a host so that the plurality of memory dies output plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way, wherein the controller is configured to determine whether to perform the correlation operation based on the number of read requests, and perform the correlation operation on the multiple read requests which are related to the same storage mode and different channels.
    Type: Application
    Filed: July 2, 2020
    Publication date: July 1, 2021
    Inventor: Jeen PARK
  • Publication number: 20210200688
    Abstract: A memory system includes a plurality of memory dies configured to store data; and a controller coupled with the plurality of memory dies through a plurality of channels, wherein the controller decides whether to perform a pairing operation, by comparing the number of pieces of read data to be outputted to an external device, which are included in a first buffer, with an output count reference value, and wherein, in the case where the number of pieces of read data stored in the first buffer is greater than or equal to the output count reference value, the controller gathers other read requests and logical addresses corresponding thereto in a second buffer, and performs the pairing operation.
    Type: Application
    Filed: July 6, 2020
    Publication date: July 1, 2021
    Inventor: Jeen PARK
  • Publication number: 20210191625
    Abstract: A memory system may include: a plurality of memory dies suitable for storing data therein; a buffer including a plurality of clusters each suitable for buffering data to be outputted to an external device; and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for: checking control information corresponding to valid clusters among the plurality of clusters, each valid cluster currently buffering data, deciding an operation margin for performing a pairing operation by calculating data processing time associated with the valid clusters based on the control information, and performing the pairing operation during the operation margin.
    Type: Application
    Filed: June 12, 2020
    Publication date: June 24, 2021
    Inventor: Jeen PARK
  • Patent number: 11036421
    Abstract: A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Jeen Park, Jung-Ae Kim, Duk-Rae Lee
  • Patent number: 11036493
    Abstract: A memory system may include: a nonvolatile memory device including a system region for storing lifespan information of a plurality of memory blocks and an one-Time Programmable (OTP) region which is not reset when firmware is upgraded; a function component configured to store the firmware; an interface configured to receive new firmware for upgrade; a validation control component configured to perform a validation operation of the nonvolatile memory device; and an upgrade component configured to upgrade the firmware when the validation operation of the nonvolatile memory device is performed, wherein the validation control component selects at least one backup block by referring to the OTP region, backs up the lifespan information to the at least one backup block, and then controls the upgrade component to upgrade the firmware.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Jeen Park