Abstract: This technology relates to a method and apparatus for improving I/O throughput through an interleaving operation for multiple memory dies of a memory system. A memory system may include: multiple memory dies suitable for outputting data of different sizes in response to a read request; and a controller in communication with the multiple memory dies through multiple channels, and suitable for: performing a correlation operation on the read request so that the multiple memory dies interleave and output target data corresponding to the read request through the multiple channels, determining a pending credit using a result of the correlation operation, and reading, from the multiple memory dies, the target data corresponding to the read request and additional data stored in a same storage unit as the target data, based on a type of the target data corresponding to the read request and the pending credit.

Abstract: A memory system may include: a plurality of memory dies suitable for storing data therein; a buffer including a plurality of clusters each suitable for buffering data to be outputted to an external device; and a controller coupled to the plurality of memory dies through a plurality of channels, and suitable for: checking control information corresponding to valid clusters among the plurality of clusters, each valid cluster currently buffering data, deciding an operation margin for performing a pairing operation by calculating data processing time associated with the valid clusters based on the control information, and performing the pairing operation during the operation margin.

Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: a command queue for queuing commands and outputting command information including information of a previous command and a subsequent command; a command detector for outputting a detection signal according to the command information; and a command generator for generating the command and outputting a management command for managing a last command immediately following the previous command in response to the detection signal.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.

Abstract: A data storage device includes a memory device and a controller. The memory device includes a plurality of planes, wherein each of the planes includes two or more memory blocks. The controller is configured to control an operation of the memory device. The controller is further configured to generate a first super block as a super block including two or more way-interleavable memory blocks among the plurality of memory blocks of the plurality of planes, determine whether each of the memory blocks included in the first super block is a bad block, retrieve a spare block for replacing a first memory block determined as a bad block, in the plurality of planes; and generate a second replacing super block as a super block in which the first memory block is replaced with a second memory block positioned in a plane which does not have the first memory block, when all spare blocks of a plane including the first memory block are used.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.

Abstract: A controller that controls a memory device, includes: a buffer memory; and a processor suitable for: temporarily storing bridge firmware data in the buffer memory when the bridge firmware data is received together with a previous firmware update request, installing and executing bridge firmware based on the bridge firmware data after approved retention firmware data is received together with a subsequent firmware update request, installing the approved retention firmware after execution of the bridge firmware, and removing the installed bridge firmware.

Abstract: Provided is an operation method of a controller which controls a memory device. The operation method may include: determining a caching order of plural pieces of map data included in a request map segment including request map data; requesting the request map segment from the memory device; marking data in a marking region which is determined based on the caching order; caching, in the caching order, the plural pieces of map data read from the memory device; and acquiring the request map data from the cached data, depending on whether the data stored in the marking region is changed.

Abstract: A memory system includes a memory device including plural non-volatile memory blocks and a controller configured to determine whether a first memory block among the plural non-volatile memory blocks is re-usable after the first memory block is determined to be a bad block and copy second block information associated with a second memory block including a second program sequence number within a set range of a first program sequence number in the first memory block to first block information of the first memory block.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.

Abstract: A memory system includes a first memory comprising at least one first code region; a second memory comprising at least one second code region; and a control unit configured to perform a first operation by executing a first code loaded to the first code region, and perform a second operation by executing a second code loaded to the second code region. The control unit performs a swap operation on the first code and the second code, based on a swap condition.

Abstract: A data storage device includes: a storage including a plurality of memory blocks; and a controller configured to control a data input/output operation on the storage according to a request from a host device, configure one or more block groups by grouping a preset number of memory blocks among the plurality of memory blocks, configure, as a short block group, a first block group having a first bad block, among the block groups, generate a bit map table based on the position of the first bad block within the short block group, and write data having a preset property to the short block group based on the bit map table.

Abstract: A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method. The embodiments receive a plurality of requests for a memory device, determine the number of hit requests and the number of miss requests with respect to the plurality of received requests, and determine whether or not to perform all or some of map data read operations for the respective miss requests in parallel and whether or not to perform all or some of user data read operations for the respective hit requests in parallel, thereby minimizing the time required for processing the plurality of requests.

Abstract: There are provided a memory controller for performing a program operation and a memory system having the memory controller. The memory system includes a memory device including first and second planes each including a plurality of m-bit (m is a natural number of 2 or more) multi-level cell (MLC) blocks; and a memory controller for allocating a first address corresponding to a first MLC block of the m-bit MLC blocks in which first m-bit MLC data is to be programmed and a second address corresponding to a second MLC block of the m-bit MLC blocks in which second m-bit MLC data is to be programmed, and transmitting the allocated addresses and logical page data included in the m-bit MLC data to the memory device. The memory controller differently determines a transmission sequence of the logical page data according to whether the addresses correspond to the same plane among the planes.

Abstract: A memory system includes a memory device including a test region; and a processor configured to write pattern data transferred from a host device to a pattern data region included in the test region, read test data from the test region, and transmit the read test data to the host device. A position of the pattern data region may be adjustable in the test region.

Abstract: A memory system includes a nonvolatile memory device and a controller configured to control the nonvolatile memory device. The nonvolatile memory device includes a first data storage region in which a memory cell stores one-bit data in a first mode and a second data storage region in which a memory cell stores two-bit or more data in a second mode. The controller controls the nonvolatile memory device to perform a read operation on the first data storage region and the second data storage region in the second mode. The controller decodes first data read from the first data storage region, and decodes second data read from the second data storage region. The controller controls the nonvolatile memory device to perform the read operation on the first data storage region in the second mode.

Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.

Abstract: A memory system includes a plurality of memory dies and a controller coupled with the plurality of memory dies via a plurality of channels. The controller is configured to perform a correlation operation on at least some read requests among a plurality of read requests inputted from an external device so that the plurality of memory dies outputs plural pieces of data corresponding to the plurality of read requests via the plurality of channels in an interleaving way. The controller is configured to determine when to perform the correlation operation based on the number of the plurality of read requests.

Abstract: A data storage device may include: a storage configured as a group of a plurality of memory blocks; and a controller configured to: control data input/output of the storage according to a request transferred from a host device; configure one or more first block groups by grouping a preset number of memory blocks which are selected at the same time among the memory blocks during an operation of the storage; configure one or more second block groups by replacing a bad memory block of the respective first block groups with a spare memory block; manage as a special block group a second block group where the spare memory block having replaced the bad memory block is not present in the same plane of the bad memory block, among the second block groups; and write data having a preset property to the special block group.