Patents by Inventor Jeff S. Brown
Jeff S. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8890564Abstract: A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.Type: GrantFiled: July 26, 2012Date of Patent: November 18, 2014Assignee: LSI CorporationInventors: Jay D. Harker, Marek J. Marasch, Jeff S. Brown, Mark F. Turner, Carol A. Anderson, Jay T. Daugherty
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Patent number: 8773192Abstract: Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.Type: GrantFiled: November 28, 2012Date of Patent: July 8, 2014Assignee: LSI CorporationInventors: Mark F. Turner, Jay Daugherty, Jeff S. Brown, Marek J. Marasch
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Publication number: 20140145775Abstract: Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: LSI CORPORATIONInventors: Mark F. Turner, Jay Daugherty, Jeff S. Brown, Marek J. Marasch
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Publication number: 20130249591Abstract: A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.Type: ApplicationFiled: July 26, 2012Publication date: September 26, 2013Applicant: LSI CORPORATIONInventors: Jay D. Harker, Marek J. Marasch, Jeff S. Brown, Mark F. Turner, Carol A. Anderson, Jay T. Daugherty
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Patent number: 8289051Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.Type: GrantFiled: November 17, 2010Date of Patent: October 16, 2012Assignee: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown, Paul Dorweiler
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Patent number: 8239801Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.Type: GrantFiled: December 31, 2008Date of Patent: August 7, 2012Assignee: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown, Joseph Simko, Miguel A. Vilchis
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Publication number: 20120194217Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown, Paul Dorweiler
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Patent number: 8209573Abstract: A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.Type: GrantFiled: December 22, 2008Date of Patent: June 26, 2012Assignee: LSI CorporationInventors: Jeff S. Brown, Mark F. Turner, Jonathan Byrn
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Publication number: 20120119785Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.Type: ApplicationFiled: November 17, 2010Publication date: May 17, 2012Applicant: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown, Paul Dorweiler
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Publication number: 20120065919Abstract: A radiation sensor for an integrated circuit (IC), a radiation sensing method and an IC incorporating the sensor or the method. In one embodiment, the radiation sensor includes: (1) a built-in self-test (BIST) controller configured to provide BIST with respect to main IC circuitry of the IC and (2) a radiation sensor controller coupled to the main IC circuitry and the BIST controller and configured to identify temporarily inactive portions of the main IC circuitry and cause the BIST controller to perform at least one BIST with respect to at least one of the portions, the at least one of the portions acting as a radiation target.Type: ApplicationFiled: September 14, 2010Publication date: March 15, 2012Applicant: LSI CorporationInventors: Jeff S. Brown, Jonathan Byrn, Mark F. Turner
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Patent number: 8135976Abstract: A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a digital control stream and (2) clock logic circuitry having a first input configured to receive a clock signal and a second input configured to receive the digital control stream. The clock logic circuitry is configured to provide a modulated clock signal in response to the clock signal and the digital control stream, wherein the modulated clock signal has an effective frequency that differs from the first frequency.Type: GrantFiled: December 17, 2008Date of Patent: March 13, 2012Assignee: LSI CorporationInventors: Jeff S. Brown, Mark F. Turner, Jonathan Byrn, Paul Dorweiler
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Patent number: 8115531Abstract: A D flip-flop (DFF), a method of operating a DFF, a latch and a library of standard logic elements including standard logic elements corresponding to a DFF and a latch. In one embodiment, the DFF has a data input and a data output and includes: (1) a master stage passgate coupled to the data input, (2) a master stage coupled to the master stage passgate and having a hysteresis inverter with feedback transistors of opposite conductivity, (3) a slave stage passgate coupled to the master stage and (4) a slave stage coupled between the slave stage passgate and the data output and having a hysteresis inverter with feedback transistors of opposite conductivity.Type: GrantFiled: March 31, 2008Date of Patent: February 14, 2012Assignee: LSI CorporationInventors: Jeff S. Brown, Miguel A. Vilchis, Mark F. Turner
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Patent number: 8055467Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.Type: GrantFiled: December 17, 2008Date of Patent: November 8, 2011Assignee: LSI CorporationInventors: Jeff S. Brown, Marek Marasch, John Gatt
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Patent number: 7932762Abstract: A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.Type: GrantFiled: December 18, 2008Date of Patent: April 26, 2011Assignee: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown
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Publication number: 20100169850Abstract: Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes: (1) a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed, (2) a circuit parser configured to identify nodes of the model and (3) a circuit evaluator configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Applicant: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown, Joseph Simko, Miguel A. Vilchis
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Publication number: 20100162058Abstract: Disclosed herein is a sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes: (1) an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and (2) a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: LSI CorporationInventors: Jeff S. Brown, Mark F. Turner, Jonathan Byrn
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Publication number: 20100156494Abstract: A single-path latch, a dual-path latch, a method of operating a DFF and a library of cells. In one embodiment, the single-path latch includes: (1) a passgate coupled to the data input, (2) a feedback path coupled to the passgate, the data output coupled thereto and (3) tristate circuitry coupled to the passgate and having a single transistor pair of opposite conductivity coupled to Boolean logic gates, the Boolean logic gates configured to control operation of the single transistor pair based on the data input and a pulse clock signal to drive the feedbacks path.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Applicant: LSI CorporationInventors: Mark F. Turner, Jeff S. Brown
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Publication number: 20100150271Abstract: A modulated clock, a method of providing a modulated clock signal, an integrated circuit including a modulated clock and a library of cells including a modulated clock. In one embodiment, the modulated clock includes (1) a clock controller configured to generate a digital control stream and (2) clock logic circuitry having a first input configured to receive a clock signal and a second input configured to receive the digital control stream. The clock logic circuitry is configured to provide a modulated clock signal in response to the clock signal and the digital control stream, wherein the modulated clock signal has an effective frequency that differs from the first frequency.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: LSI CorporationInventors: Jeff S. Brown, Mark F. Turner, Jonathan Byrn, Paul Dorweiler
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Publication number: 20100153056Abstract: A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Applicant: LSI CorporationInventors: Jeff S. Brown, Marek Marasch, John Gatt
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Patent number: 6950352Abstract: A method and apparatus is provided for replacing defective storage cells within a memory device having twisted bit lines. If a defective storage cell is discovered, the row containing that storage cell can be re-mapped to the neighboring row or the memory array. Each successive neighboring row is also re-mapped to succeeding neighboring rows by incrementing or decrementing the row addresses. This will cause the addresses to essentially shift one address value toward the redundant set of rows, and one redundant row will be subsumed for every defective row within the array. Whenever an address is shifted across a twist region, the data of that address is purposely inverted in binary voltage value (i.e., converted from a binary 1 to a binary 0, and vice versa) to accommodate the twisting of the true and complementary bit line locations.Type: GrantFiled: November 18, 2003Date of Patent: September 27, 2005Assignee: LSI Logic CorporationInventors: Chang Ho Jung, Jeff S. Brown