INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR
One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.
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This application is a continuation of U.S. patent application Ser. No. 12/947,948, entitled “INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR”, filed on Nov. 17, 2010. The above-listed application is commonly assigned with the present invention and is incorporated herein by reference as if reproduced herein in its entirety.
TECHNICAL FIELDThis application is directed, in general, to integrated circuit chip design, and more specifically to input/output core design, and a method of manufacture therefore.
BACKGROUNDInput/Output core (I/O) designers physically design their I/O's to pack the most connections between the IC and the package in the smallest amount of area. Over time, IC interfaces have become a limiting factor, as many packages require the chip I/O's to be surrounding the functional area of the IC along the outer edges of the die. Unfortunately, area grows faster than the length of the periphery of the die. For instance, when comparing a die that is one cm on a side to a die that is two cm on a side, the two cm die will have roughly four times the area for logic (four square centimeters versus one square centimeter) but only two times the periphery for I/O (8 cm versus 4 cm). Because of this, I/O's have tended to be physically designed tall and skinny—the narrower the better—to maximize the number of connections possible in the same amount of length along the perimeter of the die.
The tall and skinny I/O layout requires the I/O be rotated 90 degrees for placement along the sides of the die, and 180 degrees for placement along the top of the die. Of recent, however, process design rules have added constraints to the physical layout of the transistors on a die, one of which is that all transistor gates must be oriented in the same direction (e.g., vertical). It is difficult, however, to accommodate these constraints. For example, the orientation constraint can be accommodated by designing a special I/O layout for each side of the die, one that has the tall and skinny layout with the transistors similarly oriented. This is undesirable because of the time and expense required to do such. Alternatively, the orientation constraint can be accommodated by not rotating the I/O by 90 degrees along the sides of the design, thereby effectively making the I/O short and fat along the sides, and thereby reducing the number of I/O's surrounding the chip. This is undesirable for obvious reasons.
Accordingly, what is needed in the art is an I/O design that addresses the problems experienced by current I/O designs, including one that accommodates the need for symmetric transistor layout, while maintaining or even improving I/O packing density.
SUMMARYOne aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, and a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.
In another aspect, a method for manufacturing the aforementioned input/output cell is provided. In yet another aspect, an integrated circuit chip is provided. The integrated circuit chip, in this example, includes core logic circuitry positioned over a substrate and within a core logic layout boundary delineated on the substrate, and an array of input/output cells substantially surrounding and abutting the core logic layout boundary. In this example, each of the input/output cells includes input/output transistors oriented in a same direction as the other input/output transistors in the array. Moreover, each input/output cell in this example further includes 1) an input/output layout boundary delineated on the substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides, 2) first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides, 3) first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides, and 4) a bond pad located within the input/output layout boundary over the substrate.
Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The present disclosure is based in part, on the acknowledgement that by using a simple set of layout rules, a single I/O cell design can be used for all four sides of a core logic die, without violating transistor gate directionality rules, and maintaining or improving I/O cell density. With this acknowledgement, the disclosure recognizes that by making the power and ground conductors (e.g., rails) connectable on all four sides of the I/O layout boundary, the I/O cells can be stacked both vertically and horizontally. In concert with the power and ground conductors being connectable on all four sides, a pair of signal pins may be located on two perpendicular sides of the I/O layout boundary, also allowing the I/O cells to be stacked vertically and horizontally. The disclosure has also recognized that by making the bond pad layout boundary square, and in one example positioned in a corner of the I/O cell, improved I/O cell density can be obtained. Similar benefits are achieved by making the I/O layout boundary square.
Turning to
Delineated on the substrate 110 in the embodiment of
The term “I/O layout boundary” as used herein, means an actual or theoretical boundary encompassing all the features of a single, and often repeatable, I/O cell. For instance, certain embodiments exist wherein an array of I/O cells are stacked both horizontally and vertically around core logic circuitry. In this embodiment, a physical boundary between the different I/O cells may not exist, as they are all being formed on the same substrate. Notwithstanding the absence of a physical boundary, each of the different I/O cells would undoubtedly still have an I/O layout boundary.
The I/O cell 100 of
The I/O cell 100 of
The I/O cell of
In the embodiment of
In the embodiment of
The I/O cell 100 of
An I/O cell, such as the I/O cell 100 of
Turning to
Turning to
As discussed above with regard to the I/O boundary of
The IC chip 400 of
In accordance with one embodiment of the disclosure, each of the I/O cells 430 includes an I/O layout boundary including bond pads, as well as I/O transistors oriented in the same direction as the other I/O transistors in the first, second, third and fourth arrays 440, 450, 460, 470. Each of the I/O cells 430 additionally includes a first signal pin located proximate a side of the I/O layout boundary abutting the core logic layout boundary 420, as well as a second signal pin located proximate a side of the I/O layout boundary perpendicular the side of the I/O layout boundary abutting the core logic layout boundary 420.
Each of the I/O cells 430 may additionally include first and second power conductors extending entirely between first and second opposing sides thereof and third and fourth opposing sides thereof, respectively. Similarly, each of the I/O cells 430 may include first and second ground conductors extending entirely between first and second opposing sides thereof and third and fourth opposing sides thereof, respectively. When the I/O cells 430 are positioned in the first, second, third and fourth arrays 440, 450, 460, 470 as shown in
In the embodiment of
A fairly specific I/O cell has been described with regard to the embodiment of
Turning now to
The IC chip 500 of
Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
Claims
1. An input/output cell, comprising:
- an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;
- input/output transistors positioned within the input/output layout boundary over the substrate;
- first and second power conductors located over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides; and
- first and second ground conductors located over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides.
2. The input/output cell recited in claim 1, further including a bond pad positioned within the input/output layout boundary over the substrate.
3. The input/output cell recited in claim 2, wherein the bond pad is square.
4. The input/output cell recited in claim 2, wherein two edges of the bond pad face the input/output transistors.
5. The input/output cell recited in claim 2, wherein the bond pad is positioned proximate a corner of the input/output layout boundary.
6. The input/output cell recited in claim 1, wherein the input/output layout boundary forms a rectangle.
7. The input/output cell recited in claim 1, wherein the input/output layout boundary forms a square.
8. The input/output cell recited in claim 1, further including a first signal pin located proximate the first side and a second signal pin located proximate the third side.
9. The input/output cell recited in claim 1, wherein each of the input/output transistors is oriented in a same direction.
10. A method for manufacturing an input/output cell, comprising:
- delineating an input/output layout boundary on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides;
- positioning input/output transistors within the input/output layout boundary over the substrate;
- forming first and second power conductors over the substrate, the first power conductor extending entirely between the first and second sides and the second power conductor extending entirely between the third and fourth sides; and
- forming first and second ground conductors over the substrate, the first ground conductor extending entirely between the first and second sides and the second ground conductor extending entirely between the third and fourth sides.
11. The method recited in claim 10 further including creating a bond pad within the input/output layout boundary over the substrate, at least two edges of the bond pad facing the input/output transistors.
12. The method recited in claim 11, wherein the bond pad is square.
13. The method recited in claim 11, wherein the bond pad is positioned proximate a corner of the input/output layout boundary.
14. The method recited in claim 10, wherein the input/output layout boundary forms a square.
15. The method recited in claim 10, further including creating a first signal pin proximate the first side and a second signal pin proximate the third side.
Type: Application
Filed: Apr 10, 2012
Publication Date: Aug 2, 2012
Applicant: LSI Corporation (Milpitas, CA)
Inventors: Mark F. Turner (Longmont, CO), Jeff S. Brown (Fort Collins, CO), Paul Dorweiler (Windsor, CO)
Application Number: 13/443,691
International Classification: H03K 19/00 (20060101); H01L 21/44 (20060101);