Patents by Inventor Jefferson W. Hall
Jefferson W. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10785064Abstract: In one embodiment, a transmitter circuit may be configured to transmit a signal to a receiver. The transmitter circuit may also be configured to detect receiving energy from a transient event, for example detect a transient current, and to direct at least a portion of the energy away from the transmitted signal while the transmitter circuit is transmitting the signal.Type: GrantFiled: October 22, 2019Date of Patent: September 22, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tai-Hua Chen, Jefferson W. Hall, Florin Cornel Vladoianu, Randall Gray
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Patent number: 10700219Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.Type: GrantFiled: February 13, 2020Date of Patent: June 30, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Jefferson W. Hall
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Publication number: 20200185543Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.Type: ApplicationFiled: February 13, 2020Publication date: June 11, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mohammed Tanvir QUDDUS, Mihir MUDHOLKAR, Jefferson W. HALL
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Publication number: 20200185600Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN
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Patent number: 10608122Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the doped region with the multi-concentration impurity profile.Type: GrantFiled: March 13, 2018Date of Patent: March 31, 2020Assignee: SEMICONDUTOR COMPONENTS INDUSTRIES, LLCInventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Jefferson W. Hall
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Publication number: 20200066970Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: ApplicationFiled: August 21, 2018Publication date: February 27, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Michael J. SEDDON, Yenting WEN
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Patent number: 10573803Abstract: A semiconductor package includes a semiconductor die. A through hole in the semiconductor package and semiconductor die extends from one side of the semiconductor package and die to an opposite side of the semiconductor package and die. The through hole is configured to receive a current-carrying conductor there through. At least one current sensor is formed in, or on, the semiconductor die and configured to sense current flow in the current-carrying conductor received in the through hole.Type: GrantFiled: August 21, 2018Date of Patent: February 25, 2020Assignee: Semiconductor Components Industries, LLCInventors: Jefferson W. Hall, Michael J. Seddon, Yenting Wen
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Publication number: 20200013717Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.Type: ApplicationFiled: September 19, 2019Publication date: January 9, 2020Applicant: Semiconductor Components Industries, LLCInventors: Jefferson W. Hall, Gordon M. Grivna
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Patent number: 10461028Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.Type: GrantFiled: July 7, 2017Date of Patent: October 29, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. Hall, Gordon M. Grivna
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Publication number: 20190288125Abstract: A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.Type: ApplicationFiled: March 13, 2018Publication date: September 19, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Mohammed Tanvir QUDDUS, Mihir MUDHOLKAR, Jefferson W. HALL
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Publication number: 20190273094Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.Type: ApplicationFiled: May 17, 2019Publication date: September 5, 2019Applicant: Semiconductor Components Industries, LLCInventors: Jefferson W. Hall, Gordon M. Grivna
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Patent number: 10347656Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.Type: GrantFiled: July 7, 2017Date of Patent: July 9, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. Hall, Gordon M. Grivna
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Patent number: 10340020Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.Type: GrantFiled: September 11, 2017Date of Patent: July 2, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jefferson W. Hall
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Publication number: 20190013265Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.Type: ApplicationFiled: September 14, 2018Publication date: January 10, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. CARNEY, Jefferson W. HALL, Michael J. SEDDON
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Patent number: 10090233Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.Type: GrantFiled: July 25, 2016Date of Patent: October 2, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
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Publication number: 20180025982Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.Type: ApplicationFiled: July 7, 2017Publication date: January 25, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Gordon M. GRIVNA
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Publication number: 20180019259Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.Type: ApplicationFiled: July 7, 2017Publication date: January 18, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jefferson W. HALL, Gordon M. GRIVNA
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Publication number: 20180005705Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.Type: ApplicationFiled: September 11, 2017Publication date: January 4, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jefferson W. HALL
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Patent number: 9793002Abstract: In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.Type: GrantFiled: March 17, 2016Date of Patent: October 17, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Jefferson W. Hall
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Publication number: 20170084517Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.Type: ApplicationFiled: July 25, 2016Publication date: March 23, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. CARNEY, Jefferson W. HALL, Michael J. SEDDON