Patents by Inventor Jefferson W. Hall

Jefferson W. Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11527950
    Abstract: According to an aspect, a power supply system includes a plurality of power converters configured to deliver a system load current to a load, where the system load current is a combination of individual load currents provided by the plurality of power converters, and a system performance controller configured to detect a value of the system load current. The system performance controller is configured to determine, using power loss information, values for the individual load currents such that a composite efficiency achieves a threshold condition. The system performance controller is configured to generate control signals to operate the plurality of power converters at the determined values.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: December 13, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Patent number: 11463019
    Abstract: According to an aspect, a power supply system includes a power stage, a power supply controller configured to control operations of the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to set or adjust a control parameter for the power stage based on energy conversion efficiency of the power stage. The system performance controller includes an efficiency computation circuit configured to compute the energy conversion efficiency of the power stage based on the measured conditions, and a control manipulation module configured to modify the control parameter until the energy conversion efficiency achieves a threshold condition.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 4, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Patent number: 11355433
    Abstract: A semiconductor device having a fuse structure includes a region of semiconductor material having a major surface. A dielectric region is over the major surface. A first fuse terminal is over a first part of the dielectric region, a second fuse terminal is over a second part of the dielectric region and spaced apart from the first fuse terminal to provide a gap region, and a fuse body over a third part of the dielectric region interposed between and connected to the first fuse terminal and the second fuse terminal. A dummy structure is over the dielectric region in the gap region on a first side of the fuse body, the dummy structure spaced apart and electrically isolated from the fuse body, the first fuse terminal, and the second fuse terminal. The dummy structure is configured to reduce the presence of or reduce the effects of defects, such as cracks or voids that can emanate from the fuse structure.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: June 7, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Derryl Allman, Jefferson W. Hall
  • Patent number: 11258374
    Abstract: According to an aspect, a power supply system includes a power stage, a power supply controller configured to control operations of the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to set or adjust a control parameter for the power stage based on standby power of the power stage. The system performance controller includes a standby power computation circuit configured to compute the standby power of the power stage based on the measured conditions, and a control manipulation module configured to modify the control parameter until the standby power achieves a threshold condition.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 22, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Patent number: 11121644
    Abstract: According to an aspect, a power supply system includes a plurality of power stages configured to receive an input voltage and generate an output voltage, and a system host device connected to the plurality of power stages. The system host device includes a system performance controller configured to set or update one or more control parameters for controlling the plurality of power stages using overall energy conversion efficiency. The system host device includes an efficiency computation circuit configured to compute the overall energy conversion efficiency based on measured conditions, and a control manipulation module configured to modify the one or more control parameters until the overall energy conversion efficiency achieves a threshold condition.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: September 14, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Patent number: 11088072
    Abstract: A vertical OTP fuse formed in a semiconductor device has a substrate and an insulating layer formed over the substrate with an opening through the insulating layer extending to the substrate. A conductive layer, such as silicide, is formed over a sidewall of the opening. A resistive material, such as polysilicon, is deposited within the opening over the first conductive layer to form a first vertical OTP fuse. A plurality of vertical OTP fuses can be arranged in an array. A PN junction diode or transistor is formed in the substrate aligned with the first vertical OTP fuse. A second conductive layer is formed over the first vertical OTP fuse. The first vertical OTP fuse can be disposed between the second conductive layer and a third conductive layer. A second vertical OTP fuse can be formed over the first vertical OTP fuse for redundancy.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: August 10, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Gordon M. Grivna
  • Publication number: 20210104460
    Abstract: A semiconductor device having a fuse structure includes a region of semiconductor material having a major surface. A dielectric region is over the major surface. A first fuse terminal is over a first part of the dielectric region, a second fuse terminal is over a second part of the dielectric region and spaced apart from the first fuse terminal to provide a gap region, and a fuse body over a third part of the dielectric region interposed between and connected to the first fuse terminal and the second fuse terminal. A dummy structure is over the dielectric region in the gap region on a first side of the fuse body, the dummy structure spaced apart and electrically isolated from the fuse body, the first fuse terminal, and the second fuse terminal. The dummy structure is configured to reduce the presence of or reduce the effects of defects, such as cracks or voids that can emanate from the fuse structure.
    Type: Application
    Filed: November 5, 2019
    Publication date: April 8, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Derryl ALLMAN, Jefferson W. HALL
  • Publication number: 20210043553
    Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. CARNEY, Jefferson W. HALL, Michael J. SEDDON
  • Publication number: 20200411555
    Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Gordon M. GRIVNA
  • Patent number: 10825764
    Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
  • Patent number: 10811598
    Abstract: A sensor package includes a semiconductor die including at least one current sensor. The semiconductor die includes a first pass through hole extending from one side of the semiconductor die to an opposite side of the semiconductor die. The semiconductor package further includes a second pass through hole extending from one side of the sensor package to an opposite side of the sensor package. The second pass through hole is aligned with the first pass through hole and is configured to receive a current-carrying conductor. The at least one current sensor senses current flow in the current-carrying conductor received in the second pass through hole. An end of the current-carrying conductor is coupled to a terminal on a circuit board in the sensor package.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 20, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Michael J. Seddon, Yenting Wen
  • Patent number: 10804296
    Abstract: A monolithic semiconductor device has a substrate with a power region and control region. The substrate can be a silicon-on-insulator substrate. An opening is formed in the power region and extends partially through the substrate. A semiconductor material is formed within the opening. A power semiconductor device, such as a vertical power transistor, is formed within the semiconductor material. A control logic circuit is formed in the control region. A first isolation trench is formed in the power region to isolate the power semiconductor device and control logic circuit. A second isolation trench is formed in the control region to isolate a first control logic circuit from a second control logic circuit. An interconnect structure is formed over the power region and control region to provide electrical interconnect between the control logic circuit and power semiconductor device. A termination trench is formed in the power region.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: October 13, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Gordon M. Grivna
  • Patent number: 10797581
    Abstract: According to an aspect, a power supply system includes a power stage including a power switch and an inductor, a power supply controller connected to the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to compute an energy conversion efficiency based on the measured conditions and select a value for a zero voltage switching (ZVS) control parameter that results in the energy conversion efficiency achieving a threshold condition. The ZVS control parameter indicates a magnitude of a reverse current through the inductor to discharge a parasitic capacitance of the power switch.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 6, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Publication number: 20200313569
    Abstract: According to an aspect, a power supply system includes a power stage, a power supply controller configured to control operations of the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to set or adjust a control parameter for the power stage based on standby power of the power stage. The system performance controller includes a standby power computation circuit configured to compute the standby power of the power stage based on the measured conditions, and a control manipulation module configured to modify the control parameter until the standby power achieves a threshold condition.
    Type: Application
    Filed: August 22, 2019
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Ajay Karthik HARI
  • Publication number: 20200313538
    Abstract: According to an aspect, a power supply system includes a power stage including a power switch and an inductor, a power supply controller connected to the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to compute an energy conversion efficiency based on the measured conditions and select a value for a zero voltage switching (ZVS) control parameter that results in the energy conversion efficiency achieving a threshold condition. The ZVS control parameter indicates a magnitude of a reverse current through the inductor to discharge a parasitic capacitance of the power switch.
    Type: Application
    Filed: August 22, 2019
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Ajay Karthik HARI
  • Publication number: 20200313539
    Abstract: According to an aspect, a power supply system includes a plurality of power converters configured to deliver a system load current to a load, where the system load current is a combination of individual load currents provided by the plurality of power converters, and a system performance controller configured to detect a value of the system load current. The system performance controller is configured to determine, using power loss information, values for the individual load currents such that a composite efficiency achieves a threshold condition. The system performance controller is configured to generate control signals to operate the plurality of power converters at the determined values.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. Hall, Ajay Karthik Hari
  • Publication number: 20200313570
    Abstract: According to an aspect, a power supply system includes a plurality of power stages configured to receive an input voltage and generate an output voltage, and a system host device connected to the plurality of power stages. The system host device includes a system performance controller configured to set or update one or more control parameters for controlling the plurality of power stages using overall energy conversion efficiency. The system host device includes an efficiency computation circuit configured to compute the overall energy conversion efficiency based on measured conditions, and a control manipulation module configured to modify the one or more control parameters until the overall energy conversion efficiency achieves a threshold condition.
    Type: Application
    Filed: August 22, 2019
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Ajay Karthik HARI
  • Publication number: 20200310365
    Abstract: According to an aspect, a power supply system includes a power stage, a power supply controller configured to control operations of the power stage, a metering circuit configured to sense measured conditions of the power stage, and a system performance controller configured to be coupled to the power supply controller and the metering circuit. The system performance controller is configured to set or adjust a control parameter for the power stage based on energy conversion efficiency of the power stage. The system performance controller includes an efficiency computation circuit configured to compute the energy conversion efficiency of the power stage based on the measured conditions, and a control manipulation module configured to modify the control parameter until the energy conversion efficiency achieves a threshold condition.
    Type: Application
    Filed: August 22, 2019
    Publication date: October 1, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jefferson W. HALL, Ajay Karthik HARI
  • Patent number: 10785064
    Abstract: In one embodiment, a transmitter circuit may be configured to transmit a signal to a receiver. The transmitter circuit may also be configured to detect receiving energy from a transient event, for example detect a transient current, and to direct at least a portion of the energy away from the transmitted signal while the transmitter circuit is transmitting the signal.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 22, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tai-Hua Chen, Jefferson W. Hall, Florin Cornel Vladoianu, Randall Gray
  • Patent number: 10700219
    Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Jefferson W. Hall