Abstract: A transistor (10, 30, 60) is formed to have a body contact (16, 36, 69) that has a minimal contact to the sides of the source region (14, 34, 63). This increases the density and reduces on-resistance of the transistor (10, 30, 60).

Abstract: A power factor correction device (26, 75) stores the output of an error amplifier (32) on a storage element (39). A zero crossing detector (37) detects the zero crossings of the AC input voltage and enables the power factor correction device (26, 75) to adjust the value of the voltage stored on the storage element (39).

Abstract: An amplifier (170) includes first and second depletion mode transistors (161, 162) operating in response to first and second complementary signals (VAMP+, VAMP−), respectively, which route a first current (ISTACK1) from a first supply terminal (171) to an output (169) of the amplifier. Third and fourth depletion mode transistors (163, 164) receive the first and second complementary signals to route a second current (ISTACK2) from a second supply terminal (Ground) to the output. The first and second currents are summed to produce an output signal (VAMP2).

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A trigger circuit (22) having a depletion mode ntype transistor (32) and a depletion mode p-type transistor (34) operate by having each gate thereof driven by an independent source. When both transistors are on, the depletion mode n-type transistor (32) is driven by Is1 to Vsupply and the depletion mode p-type transistor (34) is driven by Is2 to ground. When both transistors are off, a transistor (26) is switched on driving Is1 to ground, and a transistor (28) is switched on driving the gate of depletion mode p-type transistor (34) to Vsupply. A linear regulator (50) using a depletion mode transistor pair (52, 54) with their gates thereof driven by separate sources provides a low voltage operation with minimal current leakage. One depletion mode transistor (52) is an n-type, and the second depletion mode transistor (54) is a p-type transistor.

Abstract: A regulated self-supply power controller for a switched-mode power supply includes an operational voltage supply line having a voltage magnitude that varies between two voltage magnitudes. A controllable power source is intermittently coupled to a capacitor, which is coupled to the operational voltage supply line, on the basis of the variation of the operational voltage supply line voltage magnitude between the two voltage magnitudes.

Abstract: A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).

Abstract: A semiconductor device (10,50) is disclosed which can accommodate a negative voltage on its source using a P-type substrate (12) which is connected to ground potential. A first embodiment illustrates a device which can handle high voltage applications as well as a negative voltage applied to the source. A drain contact region (29) is recessed by a dimension (X) from a first insulated region (18). The dimension (X) provides for an optimum distance for high voltage applications while avoiding lateral surface punch-through. A second embodiment illustrates a gate structure (52) having a shape which surrounds a drain contact region (62) and accommodates a high voltage application while also eliminating the lateral surface punch-through. The drain contact region (62) is formed in a P-type region (20) centered inside the gate structure (52).

Abstract: A compact metal oxide semiconductor (MOS) device has its channel region formed by the lateral extension of two high voltage (HV) regions. The two HV regions are implanted into a well region and, as a result of an annealing process, undergo outdiffusion and merge together into a single channel region. The resulting channel region has a dopant concentration that is less than the dopant concentrations of the individual HV regions. The compact MOS device exhibits a low threshold voltage characteristic.

Abstract: A switching regulator (18) for use in a switching power supply (10) detects a fault condition by looking for asserted feedback signal during a timer period. If feedback is asserted during the timer period, then the switching power supply (10) is operating normally. If feedback is not asserted during the timer period, then the switching power supply is in a fault condition. One way of implementing the timer is to charge and discharge by-pass capacitor (23). The timer period is the time for the VCC voltage to drop from a maximum value to a predetermined threshold. A counter (102) can also be used as the timer. When a fault is detected, the gate drive signal from the switching regulator is disabled for a period of time before attempting auto-restart.

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A power converter circuit (23) and a method for controlling current in a transformer (16). The power converter circuit (23) includes a controller circuit (60), a duty cycle detector circuit (61), a soft start circuit (62), and a switch (63). The switch (63) controls the current in the transformer (16). The controller circuit (60) cooperates with the soft start circuit (62) to alter the duty cycle of the switch (63). During initial start-up, the switch (63) operates at a minimum duty cycle and increases towards a maximum duty cycle to prevent transformer (16) saturation and potential failure of the switch (63). In addition, the duty cycle detector circuit (61) alters the frequency at which the switch (63) turns on and off to reduce the power consumption of the power converter circuit (23).

Abstract: A trigger circuit (22) having a depletion mode n-type transistor (32) and a depletion mode p-type transistor (34) operate by having each gate thereof driven by an independent source. When both transistors are on, the depletion mode n-type transistor (32) is driven by Is1 to Vsupply and the depletion mode p-type transistor (34) is driven by Is2 to ground. When both transistors are off, a transistor (26) is switched on driving Is1 to ground, and a transistor (28) is switched on driving the gate of depletion mode p-type transistor (34) to Vsupply. A linear regulator (50) using a depletion mode transistor pair (52, 54) with their gates thereof driven by separate sources provides a low voltage operation with minimal current leakage. One depletion mode transistor (52) is an n-type, and the second depletion mode transistor (54) is a p-type transistor.

Abstract: A metal oxide semiconductor (MOS) device (100) includes a plurality of resistive elements (108) positioned within, and surrounded by, a single active region (106). The resistive elements (108) are each formed within the single active region (106) using conductive film strips (110) as self-aligned masks, thus “bird's beak” is avoided and the accuracy of the resistive elements (108) is improved. The conductive film (110) is formed within the active region (106) directly over a thin gate oxide film (204), rather than a thick field oxide, thus essentially eliminating parasitic leakage between the resistive elements (108), and reducing the substrate area consumed by the device (100).

Abstract: A switching regulator (18) for use in a switching power supply (10) detects a fault condition by looking for asserted feedback signal during a timer period. If feedback is asserted during the timer period, then the switching power supply (10) is operating normally. If feedback is not asserted during the timer period, then the switching power supply is in a fault condition. One way of implementing the timer is to charge and discharge by-pass capacitor (23). The timer period is the time for the VCC voltage to drop from a maximum value to a predetermined threshold. A counter (102) can also be used as the timer. When a fault is detected, the gate drive signal from the switching regulator is disabled for a period of time before attempting auto-restart.

Abstract: A switching power supply (96) receives an AC voltage and converts it to a regulated DC voltage. The switching power supply (96) includes a Vcc limiter (16) to limit the operating voltage at the power supply terminal (10) of a integrated regulator circuit (118). The Vcc limiter (16) limits the operating voltage at the power supply terminal (10). When operating voltage at power supply terminal (10) increases, a differential pair of transistors (22, 24) supply a differential current to a current mirror configuration of transistors (26, 30) to supply voltage to a drive transistor (36) to increase current in the drive transistor (36) to a value based on n times the current in a reference transistor (26). An increase in current through the drive transistor (36) counteracts increased operating voltage at the power supply terminal (10), thereby reducing the operating voltage level back to a desired level.

Abstract: A controller oscillator provides a periodic output signal having first and second output level states. The oscillator is responsive to an applied saw tooth signal that varies between first and second voltages (Vlow,Vhigh). The oscillator is comprised of a comparator (82) the non-inverting input of which receives the saw tooth signal applied thereto to produce the periodic output signal at its output (86). A first voltage reference circuit (88, 90, and 92) generates the second voltage (Vhigh) that is applied to the inverting input of the comparator while the periodic output signal is at the first output level state and the input signal charges from the first voltage (Vlow) towards the second voltage. As the input signal becomes equal to the second voltage the output of the comparator switches to the second output level state and a second voltage reference (92,94, 96) provides the first voltage at the inverting input of the comparator.

Abstract: A switching regulator (18) for use in a switching power supply (10) receives a feedback signal and provides a gate drive signal. The switching regulator enables the gate drive signal once at any point during a cycle of an oscillator signal by setting a first latch (74) upon receiving a non-asserted feedback signal. Setting the first latch triggers a pulse generator (78) to generate a pulse signal. The first latch is not reset until the end of the cycle of the oscillator signal. Therefore, the pulse generator can generate only one pulse per oscillator cycle. The pulse signal sets a second latch (80) that enables the gate drive signal. The switching regulator disables the gate drive signal by resetting the second latch. A power transistor (20) conducts an inductor current through the primary winding of the transformer (16) in response to the gate drive signal.

Abstract: A switching power supply (10) uses a switching regulator (18) that is capable of operating in a dual mode with either primary side regulation or secondary side regulation. The primary and secondary side regulation schemes generate opposite phase feedback signals. The switching regulator has first (56, 62) and second (70, 74) detectors on the feedback input which detect when the feedback signal is less than a first value and also detect when the feedback signal is greater than a second value. By monitoring either case, the switching regulator can enable and disable a gate drive signal in response to opposite phases of the feedback signal and thereby regulate the switching power supply.

Abstract: A single input pin (48) provides multi-functional features for programming a power supply (10). By connecting the appropriate interface circuit (92, 100, or 112) to the single input pin (48), the power supply (10) is programmed for specific behaviors during power up and toggling of an on/off switch (96, 108). In one mode of operation a light emitting diode (106) in the interface circuit (100) is optically coupled to a microprocessor for signaling the closure of the on/off switch (108), allowing the microprocessor to control the power supply (10) through an opto-coupler (102). In another mode of operation, the single on/off switch (96) controls the power supply (10). In yet another mode of operation, Zener diode (118) in the interface circuit (112) controls the power supply (10) during brown-out and black-out conditions.