Abstract: A integrity control system uses the address bits to enable encryption and/or protection of data stored in a system memory. The encryption and protection mechanisms are coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. At least one of the address lines enabling the encryption mechanism to encrypt data before storage in the memory and to decrypt data after retrieval from memory. Another address line enables the protection mechanism to generate a hash of the data. The hash is stored and used to determine whether data has been altered while stored in system memory.

Abstract: An application specific integrated circuit (ASIC) uses a dedicated interface between core logic and an independent Serializer/De-serializer bus (SBus) to provide SBus capabilities to the core logic. In addition to the dedicated interface, the ASIC includes a controller responsive to a set of signals and a plurality of receivers distributed about the SBus. Each of the receivers is responsive to a set of commands that can be reused to test logic and support functions across each revision of the ASIC as well as to test separate ASICs with similar arrangements of support functions without requiring the generation of a distinct scan vector to test the ASIC. Additional interfaces, such as an I.E.E.E. 1149.1 interface, further extend SBus capabilities to external test equipment.

Abstract: A integrity control system uses the address bits to enable protection of data stored in a system memory. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. A subset of the address lines enables the protection mechanism to generate an integrity control value representative of the data and determine where the integrity check value is stored in a secure memory.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory.

Abstract: A debugging architecture includes a set of debug counters for counting one or more events based on a set of signals from a device being monitored. The architecture provides for observing the outputs of the debug counters during operation of the device. The outputs of the counters are provided to an output bus (e.g., a Debug Bus) via an output bus interface during operation of the device being monitored. A data gathering system can access the output bus in order to gather the data from the counters for analysis.

Abstract: Antimicrobial formulations are described that can be used to reduce levels of microbes on the surfaces of plants and plant parts.

Abstract: Antimicrobial articles that include a fatty acid monoester and an enhancer are described that are effective for killing at least 99.9% of microorganisms on the surface of the article.

Abstract: Antiviral compositions, especially those useful when applied topically, particularly to mucosal tissues (i.e., mucous membranes), including, in particular, an antiviral lipid component, such as a fatty acid ester, fatty ether, or alkoxide derivative thereof. Such compositions provide effective topical antimicrobial activity and are accordingly useful in the treatment and/or prevention of conditions that are caused, or aggravated by, microorganisms (including viruses).

Abstract: Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and, for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

Abstract: Systems and methods for providing multi-pass rendering of three-dimensional objects. A rendering pipeline that includes (N) physical texture units and one or more associated buffers emulates a rendering pipeline containing more texture units (M) than are physically present (N). Multiple rendering passes are performed for each pixel. During each texture pass only N sets of texture coordinates are passed to the texture units. The number of passes required through the pipeline to emulate M texture units is M/N, rounded up to the next integer. The N texture units of the rendering pipeline perform look-ups on a given pass for the corresponding N texture maps. The texture values obtained during the texture passes are blended by texture blenders to provide composite texture values. In successive passes, the buffers are used for temporary data and the most current composite texture values. The process is repeated until all desired texture maps are applied.

Abstract: A database correlating a specific set of linecard criteria, out of a plurality of sets of linecard criteria, to a template code is loaded into a linecard during manufacturing. A template code based on country-specific criteria is sent to the linecard at startup, wheneve otherwise desired. The template code may also be periodically refreshed from a central authority that recognizes the address of a particular linecard.

Abstract: Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and, for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.

Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory.

Abstract: Methods and systems for transparent depth sorting are described. In accordance with one embodiment, multiple depth buffers are utilized to sort depth data associated with multiple transparent pixels that overlie one another. The sorting of the depth data enables identification of an individual transparent pixel that lies closest to an associated opaque pixel. With the closest individual transparent pixel being identified, the transparency effect of the identified pixel relative to the associated opaque pixel is computed. If additional overlying transparent pixels remain, a next closest transparent pixel relative to the opaque pixel is identified and for the next closest pixel, the transparency effect is computed relative to the transparency effect that was just computed.

Abstract: A computing environment maintains the confidentiality of data stored in system memory. The computing environment has an encryption circuit in communication with a CPU. The system memory is also in communication with the encryption circuit. An address bus having a plurality of address lines forms part of the system and a value of at least one of the address lines determines a key selected from a plurality of keys to use in the encryption circuit to encrypt data being transferred by the CPU to the memory.

Abstract: A integrity control system uses the address bits to enable protection of data stored in a system memory. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. A subset of the address lines enables the protection mechanism to generate an integrity control value representative of the data and determine where the integrity check value is stored in a secure memory.

Abstract: A integrity control system uses the address bits to enable encryption and/or protection of data stored in a system memory. The encryption and protection mechanisms are coupled to the CPU by way of a data bus and to the memory by way of a data bus. An address bus that determines the location of data to be stored or retrieved from system memory has a plurality of address lines. At least one of the address lines enabling the encryption mechanism to encrypt data before storage in the memory and to decrypt data after retrieval from memory. Another address line enables the protection mechanism to generate a hash of the data. The hash is stored and used to determine whether data has been altered while stored in system memory.

Abstract: A computing environment maintains the integrity of data stored in system memory. The system has a memory management unit that maintains a plurality of real page numbers. The system also comprises an address bus in communication with the memory management unit. The address bus comprises a plurality of address lines, wherein a value of at least one address line is set by a real page number from the memory management unit. The system has an operating system that controls memory usage by controlling the real page numbers stored in said page table that is accessed by the memory management unit. At least one security feature such as data encryption is selectively applied to data stored in a page of said memory as enabled by a value of said address line set by said real page number.