Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. A process for enhancing the etch trimmability and the etch stability of features patterned on a photoresist layer is also disclosed herein. The process includes curing a photoresist layer after patterning and development but before an etch process is performed thereon. By controlling the formation of the cured portions of the features patterned on the photoresist layer, the features can be trimmed to sub-lithographic critical dimensions without pattern deformation or occurrence of other failure mechanisms.

Abstract: A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

Abstract: The invention relates to the field of manufacturing semiconductor devices, particularly processes directed to resist removal. In the method of the invention, the wafer temperature is maintained below approximately 210° C. to 220° C. to prevent residue formation, by controlling the temperature of a platen or paddle adjancent a wafer to be less than about 210° C. throughout plasma stripping of a resist layer disposed on the wafer. Moreover, to achieve a suitable yield and throughput at these temperatures, the flow rate of an additive to gases supplied to a plasma chamber to create an O2 plasma is controlled to thereby control and improve a resist striprate at these temperatures.

Abstract: A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

Abstract: A wafer having a substrate and an insulating layer over the substrate that includes a conductive layer over the insulating layer. The conductive layer mitigates charges formed on a photoresist layer during etching of features (e.g., vias and trenches). Any conductive material may serve this purpose. For example, aluminum, tantalum nitride, titanium and titanium nitride. Typically, a plasma etcher is employed for forming vias and trenches in an insulating layer to create contacts and conducting lines used to connect devices residing within different layers. The plasma etcher causes charge buildup on a photoresist layer that is utilized during the etching process. The charge buildup causes potential differences on the photoresist layer, which can lead to eventual damage of devices. A conductive layer eliminates this potential differences because a charge equilibrium is established due to the conductivity of the conductive layer.

Abstract: A method for plasma stripping a defective resist from a wafer that significantly reduces formation of residue between metal lines caused by conventional plasma stripping methodology and eliminates bridging, short-circuiting, and device failure caused thereby. The method includes locating a wafer in a chamber having a platen, reducing a pressure in the chamber to a predetermined pressure, and placing the wafer in contact with the platen to heat the wafer. In the method, the wafer is heated to a temperature below approximately 210° C. and is then moved away from the platen while the wafer temperature is below approximately 210° C. Plasma stripping a resist layer is then performed while maintaining the wafer temperature below approximately 210° C. By maintaining the temperature of the wafer below approximately 210° C., residue formation is substantially prevented and product yield is improved.

Abstract: An improved etch of thick protective topside stack films, which cover metal pads of a semiconductor device. The invention uses a downstream plasma isotropic etch to etch the topside stack film. In one embodiment, the downstream plasma isotropic etch is used to etch only part of the topside stack films. A subsequent anisotropic oxide plasma etch is used to etch the remaining topside stack film to the metal pads. In another embodiment, the downstream plasma isotropic etch is used to etch completely through the topside stack films to the metal pad. The invention allows the etching through topside stack films greater than 5 microns.

Abstract: A reduced device geometry and increased device efficiency semiconductor memory device is provided. The method of manufacturing the semiconductor memory device includes forming shallow trench isolations (STIs) on the semiconductor substrate, forming a photoresist mask over the STIs, selectively etching the STIs to form curved surface area profiles, growing a layer of tunnel oxide (TOX) over exposed areas of the semiconductor substrate, forming a first polysilicon (poly) layer over the TOX layer and the STIs, chemical-mechanical polishing (CMP) the first poly layer, forming an oxide-nitride-oxide (ONO) layer over the first poly layer, and forming a second poly layer over the ONO layer.

Abstract: Spacers are formed on a semiconductor device by depositing a spacer layer on the semiconductor device. The semiconductor device is subjected to an anisotropic etching process to leave at least a portion of the spacer layer covering the semiconductor device. The semiconductor device is then subjected to an isotropic etching process to form the spacers on the semiconductor device.

Abstract: A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

Abstract: A SiON ARC/hard mask is formed on a metal layer and patterned, thereby avoiding a separate hard mask. The use of SiON as a combined ARC/hard mask enables a reduction in the height of the metal stack, thereby reducing capacitance between metal lines and increasing circuit speed. In addition, etch marginality is improved due to the reduced aspect ratio. Embodiments include forming a thin silicon oxide layer on the SiON arc/hard mask before depositing a deep UV photoresist layer to minimize footing.

Abstract: The present invention provides improved critical dimension control on oxide films using a titanium nitride (TiN) antireflection coating (ARC). The present invention also provides for improved methods for forming more uniform local interconnects and contact holes through oxide films, by providing a TiN layer as an ARC layer. The TiN ARC layer is used in a process for etching contacts and filling the contacts with a barrier metal made out of Ti or TiN and a tungsten fill. The TiN layer is easily removed during a tungsten polish, which also removes the barrier metal. Additionally, the TiN can serve as a hardmask for the contact etch, since the chemistry is typically selective to TiN. This allows the resist to be thinned down, providing the lithography process with a larger process window.

Abstract: An anti-reflective coating layer which is used to provide better control over the photolithographic process during the contact masking step is removed using high-temperature fluorine containing chemistry to reduce the amount of thickness variations that remain after the metal contact is filled in the contact hole and planarized by polishing. As a result, post-polish defect inspections are facilitated.

Abstract: The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a plasma containing CF4+H2O to remove the photoresist mask and cleaning the contact/via opening after anisotropic etching. The CF4+H2O plasma also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping and cleaning the contact/via opening with a CF4+H2O plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.

Abstract: A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously presents a larger landing area for vias while maintaining the dimensions and intraline coupling capacitance required by design. The gaps in the patterned metal layer can be filled with a spin-on dielectric material such as spin-on glass (SOG) or hydrogen silsesquioxane (HSQ).

Abstract: A method of forming spacers in an integrated circuit is disclosed herein. The method includes providing a gate structure over a semiconductor substrate, depositing a spacer material adjacent lateral sides of the gate structure, and etching the spacer material to form spacers. The spacers have minimal surface area exposed to direct sputter.

Abstract: A bridging test structure is formed by using a modified product mask that has similar loading characteristics as an actual product mask. The modified product mask is used for devices having somewhat uniform structures, such as memory cell arrays with vertical and horizontal conductive lines. Even ones of the vertical lines are connected together by using a first horizontal line that is connected to a first test pad. Odd ones of the vertical lines are connected together by using a second horizontal line that is connected to a second test pad. Current is applied to one of the test pads to determine if that current is detected at the other test pad, and if so, a bridging problem is determined to exist.

Abstract: The invention provides an improved nitride mask etching process. The invention uses two acid baths at different temperatures to remove the nitride mask. A first bath at a higher temperature more quickly removes most of the nitride mask. The first bath can hold a higher concentration of silicon, but is less selective. A second bath at a lower temperature removes the remainder of the nitride mask. The second bath is more selective, minimizing the etch of the pad oxide. Since the second bath does less etching, defects are minimized, even though the second bath is not able to hold a higher concentration of silicon. Since only a small amount of nitride is removed, the slow etch rate of the second bath still provides a sufficient output.

Abstract: A native oxide removal process utilizes a fluorinated plasma used in a sputter etch in order to remove the native oxide prior to a cobalt oxide formation process is initiated. The fluorinated plasma, such as CF4, is performed at between 50 to 100 volts bias on a substrate on which the native oxide is to be removed, and is performed in-situ. The fluorinated plasma provides both a chemical and a physical etching of the native oxide, without harming a gate oxide layer. In a second configuration, no bias is used during the fluorinated plasma sputter etch.

Abstract: A method of writing and selectively erasing bits in a selected group of memory cells that significantly reduces the likelihood of disturbing data stored in other, non-selected groups of memory cells is disclosed. The method varies the bias voltages applied to bit lines in unselected cells depending upon the selected or non-selected state of the cells. This reduces the voltage differential applied to the unselected cells, reducing the possibility of inadvertently causing unwanted changes in the amount of charge stored on the respective floating gates of the unselected cells. The method of the present invention improves electrical isolation between columns of cells without increasing the distance between the cells.