Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer on a silicon substrate, forming an oxide on the isolation formation layer, growing a tunnel oxide layer thereon, depositing a first poly silicon layer, masking and etching the first poly silicon layer, depositing a second poly silicon layer and performing a blanket etch back step, forming an oxide/nitride/oxide layer forming a third poly-silicon layer and depositing a silicide layer thereon.

Abstract: A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

Abstract: A method of manufacturing a semiconductor device having metal structures formed on a first layer of interlayer dielectric, wherein the metal structures have a layer of TiN formed on the surface of the metal structures, a second layer of interlayer dielectric formed on and around the metal structures and layer of TiN, and a layer of photoresist formed on a surface of the second layer of interlayer dielectric. The method includes patterning and developing the layer of photoresist over selected metal structures exposing selected portions of the second layer of interlayer dielectric. The exposed portions of the second layer of interlayer dielectric are etched down to a surface of the layer of TiN and the layer of TiN is then etched down to the surface of the metal structure.

Abstract: A native oxide removal process utilizes a fluorinated plasma used in a sputter etch in order to remove the native oxide prior to a cobalt oxide formation process is initiated. The fluorinated plasma, such as CF4, is performed at between 50 to 100 volts bias on a substrate on which the native oxide is to be removed, and is performed in-situ. The fluorinated plasma provides both a chemical and a physical etching of the native oxide, without harming a gate oxide layer. The substrate is formed with nitride spacers and not oxide spacers, in order to lessen the possibility of any oxide being resputtered into the region in which the native oxide layer is being removed.

Abstract: A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

Abstract: Spin-on HSQ is employed to gap fill patterned metal layers in manufacturing ultra high density, multi-metal layer semiconductor devices. The degradation of deposited HSQ layers during formation of borderless vias, as from photoresist stripping using an O2-containing plasma, is significantly reduced or prevented by including hydrogen in the stripping plasma. Embodiments include stripping in a plasma containing a sufficient amount of a forming gas (H2/N2) to prevent reduction of the number of Si—H bonds of the deposited HSQ gap fill layer below about 70%, before and after solvent cleaning.

Abstract: A method of pad etch which removes an anti-reflective coating over a conductor in an integrated circuit is disclosed herein. The method includes providing a mask layer, stabilizing the mask layer, and providing a high temperature etch to remove the anti-reflective coating.

Abstract: A SiON ARC is formed on the uppermost metal or bonding pad layer, a topside protective layer, e.g., oxide, nitride or oxynitride, formed thereon and etching is conducted through the topside protective layer and SiON ARC to form a bonding pad opening. The use of SiON as an ARC reduces bonding pad etching time, enables a reduction in the height of the metal stack for reduced capacitance between metal lines and increased circuit speed, and improves etch marginality due to the reduced aspect ratio.

Abstract: The inventive method allows for a more complete stripping of photoresist and sidewall polymer in the production of semiconductor devices using a four step process in a plasma stripper. The first step uses CF.sub.4, O.sub.2, and H.sub.2 O as etchant gases in a downstream quartz (DSQ) chamber at a low pressure, which are ionized by radio waves for a period of between 5 and 20 seconds. The second step discontinues the radio waves, while continuing the flow of etchant gases and heating the semiconductor. The third step only provides H.sub.2 O vapor to the DSQ chamber. The fourth step provides both O.sub.2 and H.sub.2 O as etchant gases ionized by radio waves to remove the remaining resist.

Abstract: An anti-reflective coating layer which is used to provide better control over the photolithographic process during the contact masking step is removed using a boiling phosphoric acid bath to reduce the amount of thickness variations that remain after the metal contact is filled in the contact hole and planarized by polishing. As a result, post-polish defect inspections are facilitated.

Abstract: A metal feature, defined by gaps in a patterned metal layer, is formed with an inwardly tapering profile so that it is wider at the top than at the bottom. The metal feature advantageously presents a larger landing area for vias while maintaining the dimensions and intraline coupling capacitance requited by design. The gaps in the patterned metal layer can be filled with a spin-on dielectric material such as spin-on glass (SOG) or hydrogen silsesquioxane (HSQ).

Abstract: HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ surface by exposure to a plasma, such as a nitrogen-containing plasma, e.g., a plasma containing ammonia or hydrogen/nitrogen, to form a nitrided surface region. Reduction of the plasma etching rate of HSQ enables formation of reliable low resistance borderless vias.

Abstract: HSQ is employed for gap filling patterned metal layers. The surface of the deposited HSQ gap fill layer is modified to decrease its plasma etching rate. Embodiments include modifying the HSQ surface by exposure to a plasma, such as a nitrogen-containing plasma, e.g., a plasma containing ammonia or hydrogen/nitrogen, to form a nitrided surface region. Reduction of the plasma etching rate of HSQ enables formation of reliable low resistance borderless vias.

Abstract: The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal layer for gap filling leaving a non-planar upper surface. Depositing a thin layer of silicon oxide and planarizing the upper surface as by CMP, and depositing the HSQ dielectric interlayer on the planarized upper surface of the oxide layer.

Abstract: The use of HSQ as a dielectric interlayer without cracking is achieved by depositing HSQ on a planarized dielectric layer, such as a silicon oxide derived from TEOS or silane. Embodiments include depositing a first HSQ gap fill layer on a patterned metal layer for gap filling leaving a non-planar upper surface. Depositing a thin layer of silicon oxide and planarizing the upper surface as by CMP, and depositing the HSQ dielectric interlayer on the planarized upper surface of the oxide layer.

Abstract: A method of manufacturing a semiconductor wafer in a chamber having a chuck and in which temperature changes in the chamber cause residual manufacturing materials to fall onto the surface of a production wafer placed on the chuck. When the temperature of the chamber is to be changed, a protection wafer is placed on the surface of the chuck. When the temperature has been changed, the protection wafer is removed from the surface of the chuck and a production wafer is placed on the surface of the chuck and clamped. When the process is complete the production wafer is removed and the protection wafer is placed on the chuck.

Abstract: Spin-on HSQ is employed to gap fill metal layers in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of borderless vias, as from photoresist stripping using an O.sub.2 -containing plasma, is overcome by treating the degraded HSQ layer with an H.sub.2 -containing plasma to restore the dangling Si--H bonds, thereby passivating the surface and preventing moisture absorption, before filling the via opening with conductive material, such as a barrier layer.

Abstract: Patterned metal layers are gap filled with HSQ and passivated to stabilize the dielectric constant of the HSQ substantially at the as-deposited value prior to oxide deposition by PECVD and planarization. Passivation and stabilization are effected by treating the as--deposited HSQ layer in a silane (SiH.sub.4) containing plasma.

Abstract: Aluminum extrusions in overlying vias are prevented by depositing the underlying aluminum layer at a high temperature, preferably at a temperature greater than any temperature to which the wafer is exposed during subsequent processing. Embodiments include sputter depositing the underlying aluminum layer at a temperature of about 430.degree. C. to about 570.degree. C.

Abstract: Leading and trailing metal features in a dense array of conductive lines bordering an open field are formed with side surfaces that gradually taper in the direction of the open field toward an underlying substrate. Each side surface bordering the open field is formed with a sufficient slope to reduce cracking of the subsequently deposited dielectric gap fill layer at high stress areas bordering the open field.