Patents by Inventor Jeffrey A. West

Jeffrey A. West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050095843
    Abstract: Doping copper interconnects (100) with silicon (115) has been shown to improve Electromigration and Via Stress Migration reliability. After copper (118) is deposited by electrochemical deposition and chemically-mechanically polished back, doping is achieved by flowing SiH4 over the copper interconnect (100) for 0.5 to 5 seconds at a temperature of 325-425° C.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 5, 2005
    Inventors: Jeffrey West, Michael Barth, Steven Zuhoski
  • Patent number: 6841455
    Abstract: An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 11, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Paul M. Gillespie
  • Patent number: 6620343
    Abstract: The invention provides polymeric PTC compositions and electrical PTC devices with higher voltage capability and improved electrical stability. The PTC compositions of the present invention exhibit improved processability and include at a minimum an organic polymner, a conductive filler and a low molecular weight polyethylene processing aid. Depending on device design, the composition can be used in low to high voltage applications.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: September 16, 2003
    Assignee: Therm-O-Disc Incorporated
    Inventors: Edward J. Blok, Jeffrey A. West
  • Publication number: 20030127061
    Abstract: An improved flue pipe construction particularly adapted for a fuel fired water heater is disclosed which serves to reduce or minimize heat loss when the water heater is in a standby mode. The flue pipe construction comprises inner and outer concentric flue pipes which define an air space therebetween and one or more valve arrangements associated therewith to selectively restrict air flow through such air space. The valve arrangements include a thermally responsive actuator operative to open and close the valve member in response to heat generated by firing of the burner assembly without the need for any external power supply or interlocks.
    Type: Application
    Filed: January 9, 2002
    Publication date: July 10, 2003
    Inventors: Prasad S. Khadkikar, Richard L. Gerich, Christine M. Hudson, Jeffrey A. West, Derek J. Rose, Douglas J. Kempf, Douglas E. Prather, Richard E. Welch
  • Publication number: 20030122220
    Abstract: An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest
    Type: Application
    Filed: December 13, 2002
    Publication date: July 3, 2003
    Inventors: Jeffrey A. West, Paul M. Gillespie
  • Patent number: 6584940
    Abstract: An improved flue pipe construction particularly adapted for a fuel fired water heater is disclosed which serves to reduce or minimize heat loss when the water heater is in a standby mode. The flue pipe construction comprises inner and outer concentric flue pipes which define an air space therebetween and one or more valve arrangements associated therewith to selectively restrict air flow through such air space. The valve arrangements include a thermally responsive actuator operative to open and close the valve member in response to heat generated by firing of the burner assembly without the need for any external power supply or interlocks.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: July 1, 2003
    Assignee: Therm-O-Disc, Incorporated
    Inventors: Prasad S. Khadkikar, Richard L. Gerich, Christine M. Hudson, Jeffrey A. West, Derek J. Rose, Douglas J. Kempf, Douglas E. Prather, Richard E. Welch
  • Patent number: 6521975
    Abstract: An integrated circuit wafer, covered by a protective overcoat, comprising an array of integrated circuit chips bordered by seal regions and separated by dicing lines; at least two sets of substantially parallel structures within each of said seal regions, each set extending along the edge of a chip on opposite sides of each said dicing line, respectively; each of said sets comprising at least one continuous barrier wall adjacent each chip, respectively; at least one sacrificial composite structure in combination therewith, between said wall and the center of said dicing line, said composite structure being a discontinuous barrier wall comprising metal rivets interconnecting electrically conductive layers in an alternating manner, whereby said composite structure provides mechanical strength to said sets and simultaneously disperses the energy associated with crack propagation; and at least one slot opened into said protective overcoat, reaching from the surface of said overcoat at least to the surface-nearest
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: February 18, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Paul M. Gillespie
  • Patent number: 6358849
    Abstract: A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: March 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Girish A. Dixit, Manoj Jain, Eden Zielinski, Qi-Zhong Hong, Jeffrey West
  • Patent number: 6215388
    Abstract: A plurality of PTC material layers and a plurality of metal plates are sandwiched together with one adjacent pair of metal plates connected in series through one layer of PTC material. The remaining PTC material layers are connected in parallel with the one layer by selectively interconnecting the other metal plates with the one adjacent pair of metal plates.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: April 10, 2001
    Assignee: Therm-Q-Disc, Incorporated
    Inventor: Jeffrey A. West
  • Patent number: 6197220
    Abstract: The invention provides polymeric PTC compositions and electrical PTC devices with higher voltage capability and improved electrical stability. Depending on device design, the composition can be used in low to high voltage applications 6 volts up to 240 volts.
    Type: Grant
    Filed: June 6, 2000
    Date of Patent: March 6, 2001
    Assignee: Therm-O-Disc Corporation
    Inventors: Edward J Blok, Prasad Khadkikar, Jeffrey A. West, Mark R. Scoular, Joseph V. Rumler
  • Patent number: 5841341
    Abstract: A dielectric clip for holding a PTC device is dimensioned and shaped to occupy a three-dimensional space envelope that provides a close fit in a fuse socket.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: November 24, 1998
    Assignee: Therm-O-Disc, Incorporated
    Inventor: Jeffrey A. West
  • Patent number: 5691688
    Abstract: A PTC device having a PTC material sandwiched between a pair of metal plates includes a plurality of spaced-apart legs extending outwardly from the plates for reception in circuit board slots. Certain legs terminate in transverse hook portions for retaining same in a circuit board slot.
    Type: Grant
    Filed: July 20, 1994
    Date of Patent: November 25, 1997
    Assignee: Therm-O-Disc, Incorporated
    Inventors: Jeffrey A. West, Robert L. Newman
  • Patent number: 5675307
    Abstract: A thin PTC device that includes a layer of PTC material sandwiched between a pair of metal plates is provided with an increased effective thickness by outwardly extending flanges on at least one of the metal plates. This allows a close fit of the PTC device in a pocket that otherwise would be too large for holding the PTC device properly.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: October 7, 1997
    Assignee: Therm-O-Disc, Incorporated
    Inventors: John J. Krimm, Jeffrey A. West, Robert L. Newman
  • Patent number: 5570044
    Abstract: A BiCMOS power driver circuit for interfacing to a bus comprises circuitry for channelling current from a power source to the base of a bipolar device to pull the output all the way down to within a bipolar V.sub.SAT voltage drop of ground, and then uses feedback to turn-off the pull-down circuit to conserve power. A similar circuit functions to provide Incident Wave Switching and Glitch Suppression by monitoring the voltage level at the output and sinking current as necessary to maintain a low logic level.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: October 29, 1996
    Assignee: North American Philips Corporation
    Inventors: Brian C. Martin, Jeffrey A. West
  • Patent number: 5467027
    Abstract: An electronic circuit comprises a programmable cell that comprises a cell input, an output, a programmable component, programming means for selectively changing a state of the component, and coupling means for providing a signal path from the cell input to the output dependent on the component's state. The programmable component, e.g., a fuse, is located outside the signal path. Capacitances that limit the speed of operation in the read mode are considerably lower than in the prior art.
    Type: Grant
    Filed: January 25, 1993
    Date of Patent: November 14, 1995
    Assignee: North American Philips Corporation
    Inventors: Edward A. Burton, Jeffrey A. West
  • Patent number: 4584490
    Abstract: A bipolar input circuit for regulating the current/voltage level at the base of a switching transistor (QA) provides a capacitively-controlled discharge path from the base through a discharge transistor (QC) when an input signal (V.sub.I) makes certain voltage transitions. The base of the switching transistor responds to the voltage at an emitter (E1) of an input transistor (QB) which has another emitter (E2) coupled to the base of the discharge transistor. Its base is further coupled to a capacitor (C) which controls the discharge path.
    Type: Grant
    Filed: March 30, 1984
    Date of Patent: April 22, 1986
    Assignee: Signetics Corporation
    Inventor: Jeffrey A. West