Abstract: A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region.

Abstract: An integrated circuit (IC) includes a substrate having a topside semiconductor surface including active circuitry configured to provide functionality and a bottomside surface. A plurality of through substrate vias (TSVs) extend from the topside semiconductor surface to beyond the bottomside surface to provide protruding TSV tips. The TSVs include an outer dielectric liner, a metal comprising diffusion barrier layer on the dielectric liner, and a metal filler on the metal comprising barrier layer. A dielectric metal gettering layer (MGL) is on the bottomside surface lateral to and on sidewalls of the protruding TSV tips. The MGL includes at least one metal gettering agent selected from a halogen or a Group 15 element in an average concentration from 0.1 to 10 atomic %.

Abstract: Disclosed is a mousetrap having an enclosure with a rotatable top part having a downwardly extending strike plate within the enclosure, and a bottom part having an upwardly extending catch plate within the enclosure, an aperture in each of the top part and the bottom part which are in substantial alignment when the mousetrap is set, and a trigger mechanism, wherein the mousetrap is set to incapacitate or kill the mouse by the manual rotation of the top part relative to the bottom part when a mouse activates the trigger mechanism causing the top part to rotate relative to the bottom part and thereby incapacitating or killing the mouse between the strike plate and the catch plate.

Abstract: A method of forming semiconductor die includes forming a layer of polymer or a precursor of the polymer on a bottomside of a substrate having a topside including active circuitry and a bottomside, and a plurality of through-substrate-vias (TSVs). The TSVs have a liner including at least a dielectric liner and an inner metal core that extends to TSV tips that protrude from the bottomside. The layer of polymer or precursor and liner cover the plurality of TSV tips, and the layer of polymer or precursor is between the TSV tips on the bottomside. The polymer or precursor and the liner are removed from over a top of the TSV tips to reveal the inner metal core.

Abstract: An IC includes a substrate having a semiconductor top surface, a plurality of metal interconnect levels having inter-level dielectric (ILD) layers therebetween on the top surface, and a bottom surface. A plurality of through substrate vias (TSVs) extend from a TSV terminating metal interconnect level downward to the bottom surface. The plurality of TSVs include an electrically conductive filler material surrounded by a dielectric liner that define a projected volume. The projected volume includes a projected area over the electrically conductive filler material and a projected height extending upwards from the TSV terminating metal interconnect level to a metal interconnect level above, and a projected sidewall surface along sidewalls of the projected volume. A crack suppression structure (CSS) protects TSVs and includes a lateral CSS portion that is positioned lateral to the projected volume and encloses at least 80% of the projected sidewall surface.

Abstract: A non-contact voltage contrast (VC) method of determining TSV joint integrity after partial assembly. A TSV die is provided including TSVs that extend from a frontside of the TSV die to TSV tips on a bottomside of the TSV die. At least some TSVs (contacting TSVs) are attached to pads on a top surface of a multilayer (ML) package substrate. The ML package substrate is on a substrate carrier that blocks electrical access to the frontside of the TSV die. Two or more nets including groups of contacting TSVs are tied common within the ML substrate. A charged particle reference beam is directed to a selected TSV within a first net and a charged particle primary beam is then rastered across the TSVs in the first net. VC signals emitted are detected, and joint integrity for the contacting TSVs to pads of the ML package substrate is determined from the VC signals.

Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve, an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to protruding TSV tips is on a portion of the sidewalls of protruding TSV tips. The passivation layers is absent from a distal portion of protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends which cover a portion of the TSV sidewalls, are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: A method for joining integrated circuit (IC) die. The includes pressing the IC die toward a workpiece so that a protruding bonding feature is inserted into a cavity of a receptacle through an opening. The pressing bends peripheral shelf regions downward into the cavity and towards sidewall portions of the receptacle to form bent peripheral shelf regions. A protruding bonding feature contacts the bent peripheral shelf regions along a contact area. The contact area being at least primarily along the sidewall surfaces of the protruding bonding feature.

Abstract: A non-contact voltage contrast (VC) method of determining TSV joint integrity after partial assembly. A TSV die is provided including TSVs that extend from a frontside of the TSV die to TSV tips on a bottomside of the TSV die. At least some TSVs (contacting TSVs) are attached to pads on a top surface of a multilayer (ML) package substrate. The ML package substrate is on a substrate carrier that blocks electrical access to the frontside of the TSV die. Two or more nets including groups of contacting TSVs are tied common within the ML substrate. A charged particle reference beam is directed to a selected TSV within a first net and a charged particle primary beam is then rastered across the TSVs in the first net. VC signals emitted are detected, and joint integrity for the contacting TSVs to pads of the ML package substrate is determined from the VC signals.

Abstract: An electronic assembly includes an IC die including a semiconductor top surface having active circuitry thereon and a bottom surface, and at least one protruding bonding feature having sidewall surfaces and a leading edge surface extending outward from the IC die. A workpiece has a workpiece surface including at least one electrical connector and at least one framed hollow receptacle coupled to the electrical connector. The receptacle is formed from metal and includes sidewall portions and a bent top that defines a cavity. The bent top includes bent peripheral shelf regions that point downward into the cavity and towards the sidewall portions. The protruding bonding feature is inserted within the cavity of the receptacle and contacts the bent peripheral shelf regions along a contact area to form a metallic joint, wherein the contact area is at least primarily along the sidewall surfaces.

Abstract: A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes.

Abstract: Disclosed is a mousetrap having an enclosure with a rotatable top part having a downwardly extending strike plate within the enclosure, and a bottom part having an upwardly extending catch plate within the enclosure, an aperture in each of the top part and the bottom part which are in substantial alignment when the mousetrap is set, and a trigger mechanism, wherein the mousetrap is set to incapacitate or kill the mouse by the manual rotation of the top part relative to the bottom part when a mouse activates the trigger mechanism causing the top part to rotate relative to the bottom part and thereby incapacitating or killing the mouse between the strike plate and the catch plate.

Abstract: A method of fabricating IC die includes providing a substrate having a topside semiconductor surface including active circuitry and a bottomside surface. The IC die includes at least one protruding feature coupled to the active circuitry that protrudes from the bottomside surface or the topside semiconductor surface. The topside semiconductor surface and/or bottomside surface and the protruding feature are coated with a dielectric polymer. A portion of the dielectric polymer is removed from the protruding feature using a solvent to expose a tip portion of the protruding feature for electrical connection thereto. With a solvent that does not corrode or oxidize the exposed protruding feature tips, the need for a conventional subsequent chemical exposure to remove corrosion or oxidation is avoided.

Abstract: A through substrate via (TSV) die includes a plurality of TSVs including an outer dielectric sleeve and an inner metal core and protruding TSV tips including sidewalls that emerge from the TSV die. A passivation layer lateral to the protruding TSV tips is on a portion of the sidewalls of the protruding TSV tips. The passivation layers is absent from a distal portion of the protruding TSV tips to provide an exposed portion of the inner metal core. The TSV tips include bulbous distal tip ends including a first metal layer including a first metal other than solder and a second metal layer including a second metal other than solder that covers the exposed tip portion. The bulbous distal tip ends cover a portion of the TSV sidewalls and are over a topmost surface of the outer dielectric sleeve, and have a maximum cross sectional area that is ?25% more as compared to a cross sectional area of the protruding TSV tips below the bulbous distal tip ends.

Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.

Abstract: An integrated circuit (IC) device includes a substrate having a top surface including substrate pads, and a through substrate via (TSV) die including a semiconductor substrate including a topside semiconductor surface having active circuitry and a bottomside surface. The topside semiconductor surface includes bonding connectors that are coupled to the substrate pads on the top surface of the substrate. A plurality of TSVs include an inner metal core that extends from the topside semiconductor surface to protruding TSV tips which extend out from the bottomside surface. At least one of the plurality of TSVs are dummy TSVs that have their protruding TSV tips exclusive of any electrically connection thereto that provide additional surface area that enhances heat dissipation from the bottomside of the TSV die.

Abstract: An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.