Patents by Inventor Jeffrey B. Johnson
Jeffrey B. Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7265010Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.Type: GrantFiled: June 8, 2004Date of Patent: September 4, 2007Assignee: International Business Machines CorporationInventors: Peter B. Gray, Jeffrey B. Johnson
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Patent number: 7262484Abstract: A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.Type: GrantFiled: May 9, 2005Date of Patent: August 28, 2007Assignee: International Business Machines CorporationInventors: James S. Dunn, David L. Harame, Jeffrey B. Johnson, Alvin J. Joseph
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Patent number: 7253073Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.Type: GrantFiled: January 23, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Stephen S. Furkay, Jeffrey B. Johnson, Robert M. Rassel, David C. Sheridan
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Patent number: 7217628Abstract: A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.Type: GrantFiled: January 17, 2005Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: David C. Sheridan, Peter B. Gray, Jeffrey B. Johnson, Qizhi Liu
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Patent number: 7216313Abstract: A method and model for modeling a characteristic C that is distributed within a domain. A provided base equation expresses C as a function f of a variable V through use of N+1 parameters C0, C1, . . . , CN in the form C=f(C0, C1, . . . , CN, V), wherein N?1, and wherein C0, C1, . . . , CN are subject to uncertainty. A probability density function (PDF) is provided for describing the probability of occurrence of C0 in accordance with the uncertainty. Subsidiary equations expressing C1, . . . , CN in terms of C0 are provided. A value of C may be sampled by: providing a value V? of V; picking a random value C0R of C0 from the PDF; computing values C1R, . . . , CNR of C1, . . . , CN, respectively, by substituting C0R into the subsidiary equations; and calculating C by substituting C0R, C1R, . . . , CNR and V? into the base equation.Type: GrantFiled: July 30, 2004Date of Patent: May 8, 2007Assignee: International Business Machines CorporationInventors: Jeffrey B. Johnson, Bartholomew Martin, Jr.
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Patent number: 7183628Abstract: A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.Type: GrantFiled: December 7, 2004Date of Patent: February 27, 2007Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Stephen S. Furkay, Jeffrey B. Johnson, Robert M. Rassel, David C. Sheridan
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Patent number: 7135375Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.Type: GrantFiled: February 8, 2005Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohamed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan
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Patent number: 7099805Abstract: Undesirable Steiner points in tetrahedralized meshes may be minimized by tetrahedralization processes that order element subdivision based on degree of freedom data for elements in the mesh and/or treat element degree of freedom as non-static during element subdivision. Applying look-ahead, breadth-first-search subdivision, and other strategic subdivision techniques further minimizes the need for Steiner points.Type: GrantFiled: August 30, 2001Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Stephen E. Fischer, Jeffrey B. Johnson, Ralph W. Young
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Patent number: 7005665Abstract: The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first doped region flanked by a set of second doped regions; a phase change material positioned on the first doped region; and a conductor positioned on the phase change material, wherein when the phase change material is a first phase the semiconductor structure operates as a bipolar junction transistor, and when the phase change material is a second phase the semiconductor structure operates as a field effect transistor.Type: GrantFiled: March 18, 2004Date of Patent: February 28, 2006Assignee: International Business Machines CorporationInventors: Stephen S. Furkay, Hendrick Hamann, Jeffrey B. Johnson, Chung H. Lam, Hon-Sum P. Wong
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Patent number: 6927476Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.Type: GrantFiled: September 25, 2001Date of Patent: August 9, 2005Assignee: Internal Business Machines CorporationInventors: Gregory G. Freeman, Seshadri Subbanna, Basanth Jagannathan, Kathryn T. Schonenberg, Shwu-Jen Jeng, Kenneth J. Stein, Jeffrey B. Johnson
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Patent number: 6909164Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.Type: GrantFiled: November 25, 2002Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Peter B. Gray, Jeffrey B. Johnson
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Patent number: 6891251Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.Type: GrantFiled: December 18, 2002Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohammed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan
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Patent number: 6878983Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.Type: GrantFiled: December 4, 2003Date of Patent: April 12, 2005Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Stephen S. Furkay, Mohamed Youssef Hammad, Jeffrey B. Johnson
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Publication number: 20040248352Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.Type: ApplicationFiled: June 8, 2004Publication date: December 9, 2004Inventors: Peter B. Gray, Jeffrey B. Johnson
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Publication number: 20040206859Abstract: Apparatuses, systems, and methods for positioning a powered tool are provided. A support member has an adjustable length between a first end and a second end. A control device is operably coupled with the support member. The control device is configured to receive a supply of a motivating force and to receive a user input. The control device is further configured to direct at least a portion of the motivating force to the support member to direct the support member to at least one of extend or contract as indicated by the user input received. A tool bracket configured for receiving a tool is disposed at the first end of the support member is tiltable relative to a position of the support member. A base end is disposed at the second end of the support member. The base end is configured to engage a supporting surface.Type: ApplicationFiled: April 12, 2004Publication date: October 21, 2004Inventors: Ian M. Chong, Jeffrey B. Johnson
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Patent number: 6803269Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.Type: GrantFiled: August 14, 2002Date of Patent: October 12, 2004Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Stephen S. Furkay, Mohamed Youssef Hammad, Jeffrey B. Johnson
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Patent number: 6797553Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.Type: GrantFiled: July 24, 2002Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: James W Adkisson, Arne W. Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum P. Wong
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Patent number: 6744112Abstract: An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.Type: GrantFiled: October 1, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Jeffrey B. Johnson, Alvin J. Joseph, Parker A. Robinson, Raminderpal Singh, Dennis Whittaker
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Publication number: 20040099895Abstract: The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Applicant: International Business Machines CorporationInventors: Peter B. Gray, Jeffrey B. Johnson
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Publication number: 20040082124Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.Type: ApplicationFiled: December 4, 2003Publication date: April 29, 2004Applicant: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Stephen S. Furkay, Mohamed Youssef Hammad, Jeffrey B. Johnson