Abstract: An integrated circuit having structure for isolating circuit sections having at least one differing characteristic. The structure includes a chip guard ring for each circuit section having the at least one differing characteristic. Providing multiple chip guard rings allows for isolation of circuit sections and prevention of ionic contamination, but without increased expense and size. In addition, it is practicable with any IC. The invention also may include an interconnect for electrical connectivity about a chip guard ring.

Abstract: A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing.

Abstract: Undesirable Steiner points in tetrahedralized meshes may be minimized by tetrahedralization processes that order element subdivision based on degree of freedom data for elements in the mesh and/or treat element degree of freedom as non-static during element subdivision. Applying look-ahead, breadth-first-search subdivision, and other strategic subdivision techniques further minimizes the need for Steiner points.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract: A method for making a non-self-aligned, heterojunction bipolar transistor includes forming extrinsic base regions with a PFET source/drain implant aligned with the polysilicon in an emitter stack but which are not directly aligned with an emitter opening defined in that stack. This is achieved by making the emitter pedestal wider than the emitter opening. This advantageously removes the dependency of alignment between the extrinsic base regions and the emitter opening, thereby resulting in fewer process steps, reduced thermal cycles, and improved speed.

Abstract: A method of improving the speed of a heterojunction bipolar device without negatively impacting ruggedness of the device is provided. This method includes the steps of providing a structure that includes at least a bipolar device region, the bipolar device region comprising at least a collector region formed over a sub-collector region; and forming an n-type dopant region within the collector region, wherein the n-type dopant region has a vertical width that is less than about 2000 Å and a peak concentration that is greater than a peak concentration of the collector region. The present invention also provides a method of fabricating a heterojunction bipolar transistor device as well as the device itself which can be used in various applications including as a component for a mobile phone, a component of a personal digital assistant and other like applications wherein speed and ruggedness are required.

Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

Abstract: The present invention provides a unique device structure and method that provides increased transistor performance in integrated bipolar circuit devices. The preferred embodiment of the present invention provides improved high speed performance with a stepped collector dopant profile that reduces emitter-collector transit time and parasitic resistance with minimal increase in parasitic capacitances. The preferred stepped collector dopant profile includes a shallow implant and a deeper implant. The shallow implant reduces the base-collector space-charge region width, reduce resistance, and tailors the collector-base breakdown characteristics. The deeper implant links the buried collector to the subcollector and provides a low resistance path to the subcollector. The stepped collector dopant profile has minimal impact on the collector-base capacitance outside the intrinsic region of the device since the higher dopant is compensated by, or buried in, the extrinsic base dopants outside the intrinsic region.

Abstract: A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate has a plurality of spaced apart isolation regions on the substrate substantially parallel to one another. An active region is between each pair of adjacent isolation regions. The active and isolation regions are formed in parallel and in the column direction. In the row direction, strips of spaced apart silicon nitride are formed. A source line plug is formed between adjacent pairs of silicon nitride and is in contact with a first region in the active regions, and the isolation regions. The strips of silicon nitride are removed and isotropically etched. In addition, the materials beneath the silicon nitride are also isotropically etched. Polysilicon spacers are then formed in the row direction parallel to the source line plug and adjacent to the floating gates to form connected control gates. A second region is formed between adjacent, spaced apart, control gates.

Abstract: A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.

Abstract: A method of detecting electromagnetic radiation with an active pixel sensor photosensitive device having an extremely thin virtual pinning layer formed by inverting semiconductor material at the surface of a photosensitive region. The thin pinning layer improves blue light response. The inverted pinning layer is produced by connecting a negative potential source to a transparent conductive layer, preferably made of indium-tin-oxide positioned over most of the photosensitive region. The conductive layer is insulated from the photosensitive region by a thin insulating layer. Connection to the pinning layer is through a coupling region formed in an area not covered by the conductive and insulating layers. Red light response is improved and the depth of the photosensitive region reduced by creating a strained layer, preferably of germanium silicon, deep within the photosensitive region. The strained layer has a modified bandgap which increases the absorption rate of red light.

Abstract: A photosensitive device includes an array of active pixel sensor devices, each APS device being formed in an isolated cell of silicon. Each cell has an insulating barrier around it, and sits upon an insulating layer formed on an underlying substrate. A semiconductor connector making vertical contact between the pinning layer and the body of each APS device preferably replaces at least some portion of the insulating barrier adjacent to each cell. The semiconductor connector may be a single vertical connection for each cell or it may be an elongated strip connecting multiple APS devices. It may extend only to the underlying insulating layer or it may extend through the insulating layer to the substrate, with the substrate acting to interconnect and ground the pinning layer and the body of each APS device. The invention also includes the method of making the photosensitive device.

Abstract: A tool for lifting and removing heavy lids, such as manhole covers and similar articles. The tool includes an elongate lever with a handgrip at the upper end and a pivot head at the lower end. Wheels on the pivot head provide a pivot axis, with a hook being mounted in front of the pivot axis and a footplate being mounted behind the axis. The hook is inserted in an opening in the lid, and the lid is then lifted and removed by pulling back on the lever and stepping down on the footplate. After removal, the lid can be transported by rolling the assembly over the ground using the wheels. The invention thus facilitates removal and installation of heavy lids with minimal strain and potential injury to the operator.

Abstract: The present invention is a complementary active pixel sensor cell and method of making and using the same. The complementary active pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a complementary active pixel sensor cell circuit. Two active pixel sensor cell circuits, an NFET circuit and complementary PFET circuit are created for use with a photodiode. The NFET circuit captures electron current. The PFET circuit captures hole current. The sum of the currents is approximately double that of conventional active pixel sensor circuits using similarly sized photodiode regions.

Abstract: A fixture 14 for use in applying a material to a face 16,18 of a rotor blade 10 is disclosed. Various construction details are developed which reduce rework of the rotor blade and facilitate application of the material are developed. In one embodiment, a pad 48 has a surface 50 which blocks the flow of molten material to the flow path surface 42 of the shroud 12 of the rotor blade.