Abstract: A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.

Abstract: Example ferroelectric memories and storage devices are described One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.

Abstract: This application provides a magneto-resistive random access memory, to reduce a chip area. The magneto-resistive random access memory includes: a plurality of stacked stacking layers, where each stacking layer includes a plurality of magnetic memory cells arranged in a two-dimensional manner; and a plurality of selective metal layers, where each stacking layer is disposed between two selective metal layers and is adjacent to the two selective metal layers, and each selective metal layer is connected to a magnetic memory cell in an adjacent stacking layer, and is configured to perform a read/write operation on the magnetic memory cell.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.

Abstract: Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells are disclosed. In one aspect, a MOS standard cell includes supply rails disposed in a first metal layer and along respective axes in an X-axis direction. The MOS standard cell includes metal lines disposed in the first metal layer and along respective axes in the X-axis direction. The MOS standard cell includes a source region formed in a semiconductor substrate beneath the first metal layer and adjacent to a plane in an X-Z-axis direction disposed between a supply rail and the source region. The source region is electrically coupled to the corresponding supply rail. Forming the source region in this manner allows the MOS standard cell to be disposed adjacent to other MOS standard cells while achieving the minimum required source-drain tip-to-tip spacing.

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.

Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.

Abstract: Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.