Abstract: An integrated circuit structure includes a semiconductor substrate, and a phonon-screening layer over the semiconductor substrate. Substantially no silicon oxide interfacial layer exists between the semiconductor substrate and the phonon-screening layer. A high-K dielectric layer is located over the phonon-screening layer. A metal gate layer is located over the high-K dielectric layer.

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.

Abstract: A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

Abstract: Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract: A method of forming an electronic device includes forming an oxygen scavenging layer proximate to a dielectric layer in a gate region of a field effect transistor (FET). The interface layer is between the dielectric layer and a substrate of the FET. The method further includes forming a dipole layer by annealing the oxygen scavenging layer, the dielectric layer, and the interface layer.

Abstract: Electron-beam (e-beam) based semiconductor device features are disclosed. In a particular aspect, a method includes performing a first lithography process to fabricate a first set of cut pattern features on a semiconductor device. A distance of each feature of the first set of cut pattern features from the feature to an active area is greater than or equal to a threshold distance. The method further includes performing an electron-beam (e-beam) process to fabricate a second cut pattern feature on the semiconductor device. A second distance of the second cut pattern feature from the second cut pattern feature to the active area is less than or equal to the threshold distance.

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract: An electronic device includes a middle-of-line (MOL) stack. The electronic device includes a top local interconnect layer and a contact coupling the top local interconnect layer to a gate of a semiconductor device through a first dielectric layer. The electronic device also includes one or more isolation walls between the contact and the first dielectric layer, wherein the one or more isolation walls include aluminum nitride (AlN).

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active potion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract: A semiconductor device includes a transistor having a metal gate, a source, and a drain. The semiconductor device also includes a high resistance metal etch-stop layer positioned above the metal gate of the transistor. The semiconductor device also includes a metal layer formed on the high resistance metal etch-stop layer. The metal layer is positioned above at least one of the source of the transistor or the drain of the transistor.

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration.

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

Abstract: A semiconductor device includes a dielectric material and an interconnect structure. The semiconductor device further includes a barrier layer positioned between the dielectric material and the interconnect structure. The barrier layer includes two or more metals. Each metal of the two or more metals of the barrier layer is phase segregated from each other metal of the two or more metals.

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.