Image Sensor with Extension Pad
The present disclosure describes an image sensor and a method for forming the image sensor. The image sensor includes an image sensing element disposed on a substrate, an extension pad disposed adjacent to the image sensing element, and a polysilicon pillar disposed on the extension pad. The image sensor further includes an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.
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Semiconductor image sensors are used to sense radiation, such as light, and convert the sensed radiation into electrical signals. Semiconductor image sensors utilize an array of pixels, such as photodiodes, to sense radiation that is projected toward the pixels. These image sensors can include extension pads for electrical connections. Complementary metal-oxide-semiconductor (CMOS) image sensors are used in various applications, such as digital still cameras and mobile phone cameras.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the embodiments and/or configurations discussed herein.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.
In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.
The discussion of elements in
Complementary metal-oxide-semiconductor (CMOS) image sensors are used in various applications, such as digital still cameras and mobile phone cameras. CMOS image sensors can include an array of image sensing elements or pixels, such as photodiodes. The pixels can sense radiation, such as light, that is projected toward the pixels. CMOS image sensors can further include extension pads for electrical connections. The extension pads can be large in size. For example, an extension pad with a square shape can have a side length of about 80 μm. Because of the large size of the extension pads, during a chemical mechanical planarization (CMP) process to form the extension pads, a curved surface of the extension pads can be formed relative to a front surface of the substrate on which the image sensor is formed. The curvature of the curved surface of the extension pads can increase after a CMP process to form shallow trench isolation (STI) structures. After an interlayer dielectric (ILD) layer is deposited on the image sensing elements and the extension pads, the ILD layer can be polished by a CMP process. Because of the curved surface of the extension pads, the polished ILD layer can have a nonuniform surface after the CMP process. The polished ILD layer can have a nonuniform surface if a distance between a highest point on the polished ILD layer and a lowest point on the polished ILD layer is greater than about 600 nm. The nonuniform ILD layer can cause fabrication challenges when an interconnect structure is formed in the ILD layer. For example, some metal line openings may be disconnected from some metal via openings. The nonuniform ILD layer can increase electrical connection failures of the interconnect structure. The nonuniform ILD layer can also increase bonding failures after the image sensors are bonded to another substrate containing application-specific circuits. The increased electrical connection failures and the increased bonding failures can reduce device performance and reliability.
The present disclosure provides an example image sensor with an ILD layer with improved uniformity and an example method for fabricating the same. In some embodiments, polysilicon pillars can be formed on the extension pads. The polysilicon pillars can provide structural support for the ILD layer deposited on the extension pads. The polysilicon pillars can reduce the polishing speed of the ILD layer deposited in or around the curved surface of the extension pads. Consequently, the polysilicon pillars can improve the polishing uniformity of the ILD layer across the image sensor. In some embodiments, a distance between a highest point on the polished ILD layer and a lowest point on the polished ILD layer can be less than about 400 nm. In some embodiments, the polysilicon pillars on the extension pads can form a slot region. The slot region can be away from the polysilicon pillars. The slot region can be a rectangular region. The slot region can be used to connect the interconnect structure to the extension pads. The slot region can also be used to bond a wire to the extension pads. In some embodiments, polysilicon pillars can also be formed in an area on the image sensor that is away from the array of pixels. The polysilicon pillars in the area away from the array of pixels can improve the uniformity of the ILD layer in that area. The polysilicon pillars on the extension pads and in the area away from the array of pixels can increase the polishing uniformity of the ILD layer. The uniform ILD layer can reduce electrical connection failures of the interconnect structure. The uniform ILD layer can also reduce bonding failures after the image sensors are bonded to another substrate containing application-specific circuits. The decreased electrical connection failures and the decreased bonding failures can improve device performance and reliability.
Image sensor 200 can include extensions pads 204. Extension pads 204 can be along a side portion of image sensor 200. Extension pads can be large in size. For example, extension pads 204 with a square shape can have a side length of about 80 μm. The large size of extension pads 204 can cause a nonuniform ILD layer in subsequent operations. In some embodiments, polysilicon pillars (not shown in
In some embodiments, polysilicon pillars 208 can have a square or a rectangular cross section. Polysilicon pillars 208 can have a width W1 between about 5 nm and about 10 nm, between about 3 nm and about 15 nm, and between about 1 nm and about 20 nm. Polysilicon pillars 208 can have a length L1 between about 5 nm and about 10 nm, between about 3 nm and about 15 nm, and between about 1 nm and about 20 nm. If W1 or L1 is less than about 1 nm, polysilicon pillars 208 cannot provide sufficient physical support to reduce the CMP nonuniformity of the ILD layer. If W1 or L1 is greater than about 20 nm, polysilicon pillars 208 can consume too much space which can increase the size of image sensor 200. In some embodiments, polysilicon pillars 208 can have other cross-sectional shapes, such as a circular shape, an oval shape, a trapezoidal shape, a diamond shape, and an irregular shape. In some embodiments, polysilicon pillars 208 can have rounded corners between adjacent sidewalls. In some embodiments, polysilicon pillars 208 can have rounded top portions.
In some embodiments, slot regions 210 can be a square or a rectangular region. Slot regions 210 can have a width W2 between about 3 μm and about 5 μm, between about 2 μm and about 8 μm, and between about 1 μm and about 10 μm. Slot regions 210 can have a length L2 between about 50 μM and about 60 μM, between about 40 μm and about 70 μM, and between about 30 μm and about 80 μm. If W2 is less than about 1 μm or L2 is less than about 30 μm, slot regions 210 cannot provide sufficient space for the interconnect structures and the wires. If W2 is greater than about 10 μm or L2 is greater than about 80 μm, slot regions 210 can consume too much space which can increase the size of image sensor 200. In some embodiments, slot regions 210 can have other shapes, such as a circular shape, an oval shape, a trapezoidal shape, a diamond shape, and an irregular shape.
In some embodiments, extension pad 204 can have a square or a rectangular shape. Extension pad 204 can have a width W3 between about 70 μm and about 90 μM, between about 60 μm and about 120 μm, and between about 50 f IM and about 150 μM. Extension pad 204 can have a length L3 between about 70 μm and about 90 μm, between about 60 μm and about 120 μm, and between about 50 μm and about 150 μm. If W3 or L3 is less than about 50 μm, extension pad 204 cannot provide sufficient space for the interconnect structures and the wires. If W3 or L3 is greater than about 150 μM, extension pad 204 can consume too much space which can increase the size of image sensor 200. In some embodiments, extension pad 204 can have other shapes, such as a circular shape, an oval shape, a trapezoidal shape, a diamond shape, and an irregular shape.
First substrate 140 and second substrate 102 can be a semiconductor material, such as Si, germanium (Ge), silicon germanium (SiGe), a SOI structure, and combinations thereof. Further, first substrate 140 and second substrate 102 can be doped with p-type dopants, such as boron (B), indium (In), aluminum (Al), and gallium (Ga), or n-type dopants, such as phosphorous (P), and arsenic (As). First substrate 140 can have a height of about 3 μm.
First ILD layer 130, second ILD layer 106, DTI structure 142, STI structure 141, and passivation layer 143 can include an insulating material, such as silicon oxide (SiOx), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide (SiGeOx).
Metal vias 132A and 108A and metal lines 132B and 108B can include a suitable conductive material, such as tungsten (W), molybdenum (Mo), nickel (Ni), bismuth (Bi), scandium (Sc), titanium (Ti), copper (Cu), cobalt (Co), silver (Ag), aluminum (Al), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten nitride (WN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and combinations thereof. The first interconnect structure including metal vias 132A and metal lines 132B and the second interconnect structure including metal vias 108A and metal lines 108B can electrically couple first chip 460 to second chip 470.
Barrier layer 139 can include any suitable materials, such as a metal oxide (MOx, a metal nitride (MNx), a metal carbide (MG), a metalaluminate (MAlxOy), a combination of metal oxides (M1Ox/M2Ox), a metal-silicate (MSiOx), and combinations thereof. In some embodiments, the metal in the above-mentioned materials is a transition metal, such as hafnium (Hf), Zr, Ti, and Al, a rare earth metal, such as yttrium (Y), ytterbium (Yb), erbium (Er), and combinations thereof. In some embodiments, barrier layer 139 can include dielectric materials, such as SiN, SiOCN, SiCN, other suitable insulating materials, and combination thereof. In some embodiments, the thickness of barrier layer 139 can be between about 1 nm and about 10 nm.
Transfer transistor 134 and application-specific circuit 104 can include a gate structure. The gate structure can include multiple layers (not shown in
Diffusion well 136 can be a doped region disposed in substrate 140 that functions as a source/drain (S/D) region. Diffusion well 136 can include a semiconductor material, such as Si and SiGe. Diffusion well 136 can be doped with p-type dopants, such as B and other suitable p-type dopants. Diffusion well 136 can be doped with n-type dopants, such as P and other suitable n-type dopants. A dopant concentration of diffusion well 136 can be in a range from about 1×1020 atoms/cm3 to about 3×1022 atoms/cm3. In some embodiments, diffusion well 136 can have a depth of about 50 nm to about 70 nm. Diffusion well 136 can be adjacent to transfer transistor 134. Application-specific circuit 104 can include S/D regions (not shown in
Photodiode 138 can include two oppositely-doped regions disposed in substrate 140. For example, photodiode 138 can include a first doped region 138A and a second doped region 138B. First doped region 138A and second doped region 138B can include a semiconductor material, such as Si and SiGe. First doped region 138A can be n-doped and second doped region 138B can be p-doped. Alternatively, first doped region 138A can be p-doped and second doped region 138B can be n-doped. N-doped regions can be doped with n-type dopants, such as P and other suitable n-type dopants. P-doped regions can be doped with p-type dopants, such as B and other suitable n-type dopants. A dopant concentration of first doped region 138A and second doped region 138B can be in a range from about 1×1020 atoms/cm3 to about 3×1022 atoms/cm3, from about 0.8×1020 atoms/cm3 to about 3.3×1022 atoms/cm3, and from about 0.5×1020 atoms/cm3 to about 3.5×1022 atoms/cm3. If the dopant concentration is less than about 0.5×1020 atoms/cm3, photodiode 138 cannot effectively sense radiation. Photodiode 138 cannot effectively sense radiation if the total generated photocurrent density is below about 10 nA/cm2. If the dopant concentration is greater than about 3.5×1022 atoms/cm3, the manufacturing cost of forming photodiode 138 can be too high.
Polysilicon pillars 208 can include a polysilicon material. In some embodiments, polysilicon pillars 208 can include other materials, such as a dielectric material, a metal, and a metal compound. Polysilicon pillars 208 can be formed in an area that is away from pixels 206, such as area 203. ILD layer 130 deposited in area 203 has less physical support from pixels 206 and would polish faster. Polysilicon pillars 208 can be formed on extension pad 204. ILD layer 130 deposited on extension pad 204 has less physical support because of curved surface 205 of extension pad 204 and would polish faster. Polysilicon pillars 208 can provide structural support for ILD layer 130 deposited in area 203 and on extension pad 204. Polysilicon pillars 208 can reduce the polishing speed of ILD layer 130 deposited in area 203 and on extension pad 204. Consequently, polysilicon pillars 208 can improve the polishing uniformity of ILD layer 130 across image sensor 400. In some embodiments, a distance between a highest point on the polished ILD layer 130 and a lowest point on the polished ILD layer 130 can be less than about 400 nm. Polysilicon pillars 208 on extension pad 204 can form slot regions 210. Slot regions 210 are away from polysilicon pillars 208 and can be used to electrically connect to the first interconnect structure, including metal vias 132A and metal lines 132B and wire 145.
Polysilicon pillars 208 can have a height H1 between about 600 nm and about 800 nm, between about 400 nm and about 1000 nm, and between about 200 nm and about 1200 nm. If H1 is less than about 200 nm, polysilicon pillars 208 cannot provide sufficient physical support to reduce the CMP nonuniformity of ILD layer 130. If H1 is greater than about 1200 nm, polysilicon pillars 208 can consume too much space which can increase the size of image sensor 400.
Extension pad 204 can include a suitable conductive material, such as W, Ti, Ag, Ru, Mo, Cu, Co, Al, Ir, Ni, metal alloys, and combinations thereof. Extension pad 204 can have a height of about 1 μm. Extension pad 204 can have curved surface 205 with a curvature between about 0.05 μm−1 and about 1 μm−1. Curved surface 205 can be formed during formation of extension pad 204. The curvature of curved surface 205 can increase during the formation of STI structure 141. Without polysilicon pillars 208, curved surface 205 can cause high nonuniformity of ILD layer 130 after CMP. Polysilicon pillars 208 on extension pad 204 can increase the polishing uniformity of ILD layer 130. The uniform ILD layer 130 can reduce electrical connection failures of the first interconnect structure including metal vias 132A and 132B. The uniform ILD layer 130 can also reduce bonding failures after first chip 460 is bonded to second chip 470. The decreased electrical connection failures and the decreased bonding failures can improve device performance and reliability.
Wire 145 can include a suitable conductive material, such as W, Ti, Ag, Ru, Mo, Cu, Co, Al, Ir, Ni, metal alloys, and combinations thereof. Wire 145 can be bonded to extension pad 204. Wire 145 can be bonded to slot region 210 of extension pad 204. Wire 145 can be placed in wire bonding opening 147. Wire bonding opening 147 can be formed through passivation layer 143, first substrate 140, and extension pad 204. Barrier layer 139 can be disposed in wire bonding opening 147. In some embodiments, wire bonding opening 147 can be filled with a solder bump (not shown in
Color filter 144 can include a color photoresist disposed on passivation layer 143. The color photoresist can include pigments or dyes. Color filter 144 can transmit radiation having wavelengths within a range. For example, color filter 144 can pass red, blue, or green light to photodiode 138. In some embodiments, color filter 144 across image sensor 400 can transmit radiation having the same wavelength. In some embodiments, color filter 144 across image sensor 400 can transmit radiation having different wavelengths. In some embodiments, there can be a grid structure (not shown in
Micro lens 146 can include a polymer material with a round shape and disposed on color filter 144. Micro lens 146 can focus the incident radiation towards photodiode 138.
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The present disclosure provides an example image sensor (e.g., image sensor 400) with an ILD layer (e.g., first ILD layer 130) with improved uniformity and an example method (e.g., method 500) for fabricating the same. In some embodiments, polysilicon pillars (e.g., polysilicon pillars 208) can be formed on the extension pads (e.g., extension pad 204). The polysilicon pillars can provide structural support for the ILD layer deposited on the extension pads. The polysilicon pillars can reduce the polishing speed of the ILD layer deposited in or around the curved surface (e.g., curved surface 205) of the extension pads. Consequently, the polysilicon pillars can improve the polishing uniformity of the ILD layer across the image sensor. In some embodiments, a distance between a highest point on the polished ILD layer and a lowest point on the polished ILD layer can be less than about 400 nm.
In some embodiments, the polysilicon pillars on the extension pads can form a slot region (e.g., slot region 210). The slot region can be away from the polysilicon pillars. The slot region can be a rectangular region. The slot region can be used to connect the interconnect structure (e.g., the first interconnect structure including metal vias 132A and metal lines 132B) to the extension pads. The slot region can also be used to bond a wire (e.g., wire 145) to the extension pads.
In some embodiments, polysilicon pillars can also be formed in an area on the image sensor that is away from the array of pixels. The polysilicon pillars in the area away from the array of pixels can improve the uniformity of the ILD layer in that area. The polysilicon pillars on the extension pads and in the area away from the array of pixels can increase the polishing uniformity of the ILD layer. The uniform ILD layer can reduce electrical connection failures of the interconnect structure. The uniform ILD layer can also reduce bonding failures after the image sensors are bonded to another substrate (e.g., second substrate 102) containing application-specific circuits (e.g., application-specific circuit 104). The decreased electrical connection failures and the decreased bonding failures can improve device performance and reliability.
In some embodiments, an image sensor includes an image sensing element disposed on a substrate, an extension pad disposed adjacent to the image sensing element, and a polysilicon pillar disposed on the extension pad. The image sensor further includes an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.
In some embodiments, an image sensor includes an array of image sensing elements disposed at a center portion of a chip, a plurality of extension pads disposed along a side portion of the chip, and a plurality of polysilicon pillars disposed on each extension pad of the plurality of extension pads. The image sensor further includes an interlayer dielectric (ILD) layer disposed over the array of image sensing elements, the plurality of extension pads, and the plurality of polysilicon pillars.
In some embodiments, a method includes forming an image sensing element on a substrate, forming an extension pad adjacent to the image sensing element, and forming a polysilicon pillar on the extension pad. The method further includes depositing an insulating layer over the image sensing element, the extension pad, and the polysilicon pillar. The method further includes polishing the insulating layer by a chemical mechanical planarization (CMP) process and forming an interconnect structure within the insulating layer and electrically coupled to the extension pad.
It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way.
The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. An image sensor, comprising:
- an image sensing element disposed in a substrate;
- an extension pad disposed adjacent to the image sensing element;
- a polysilicon pillar disposed on the extension pad; and
- an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.
2. The image sensor of claim 1, wherein the image sensing element comprises:
- a photodiode comprising an n-type region and a p-type region adjacent to the n-type region; and
- a transfer transistor, a diffusion well, a source follower, a reset transistor, a row select transistor, and an in-pixel circuit, wherein the in-pixel circuit comprises a column amplifier, a correlated double sampling (CDS) circuit, and combinations thereof.
3. The image sensor of claim 1, wherein the extension pad comprises a curved surface relative to a front surface of the substrate.
4. The image sensor of claim 1, wherein the polysilicon pillar has a height between about 500 nm and about 900 nm and a square cross section with a side length between about 2 nm and about 10 nm.
5. The image sensor of claim 1, further comprising an other polysilicon pillar disposed adjacent to the extension pad.
6. The image sensor of claim 1, wherein a distance between a highest point on the insulating layer and a lowest point on the insulating layer is less than about 400 nm.
7. The image sensor of claim 1, further comprising:
- an interconnect structure disposed within the insulating layer and electrically coupled to the extension pad; and
- a wire bonded to the extension pad to electrically couple the interconnect structure to a backside of the substrate.
8. The image sensor of claim 7, wherein the interconnect structure and the wire are disposed in an area away from the polysilicon pillar.
9. The image sensor of claim 1, further comprising an other substrate bonded to the substrate, wherein the other substrate comprises an application-specific circuit comprising an analog-to-digital converter (ADC), a counter, a memory storage device, and combinations thereof.
10. The image sensor of claim 1, further comprising:
- an isolation structure disposed adjacent to the image sensing element;
- a passivation layer disposed on the image sensing element and the isolation structure;
- a color filter disposed on the passivation layer; and
- a micro lens disposed on the color filter.
11. An image sensor, comprising:
- an array of image sensing elements disposed at a center portion of a chip;
- a plurality of extension pads disposed along a side portion of the chip;
- a plurality of polysilicon pillars disposed on each extension pad of the plurality of extension pads; and
- an interlayer dielectric (ILD) layer disposed over the array of image sensing elements, the plurality of extension pads, and the plurality of polysilicon pillars.
12. The image sensor of claim 11, wherein each extension pad of the plurality of extension pads comprises a curved surface relative to a front surface of the chip.
13. The image sensor of claim 11, wherein each extension pad of the plurality of extension pads comprises a slot region, wherein the slot region is away from the plurality of polysilicon pillars.
14. The image sensor of claim 11, wherein each polysilicon pillar of the plurality of polysilicon pillars has a height between about 500 nm and about 900 nm and a square cross section with a side length between about 2 nm and about 10 nm.
15. The image sensor of claim 11, further comprising an other plurality of polysilicon pillars disposed in an area at the center portion of the chip that is away from the array of image sensing elements.
16. The image sensor of claim 11, further comprising:
- an interconnect structure disposed within the ILD layer and electrically coupled to the plurality of extension pads; and
- a wire bonded to the plurality of extension pads to electrically couple the interconnect structure to a backside of the chip.
17. A method, comprising:
- forming an image sensing element on a substrate;
- forming an extension pad adjacent to the image sensing element;
- forming a polysilicon pillar on the extension pad;
- depositing an insulating layer over the image sensing element, the extension pad, and the polysilicon pillar;
- polishing the insulating layer by a chemical mechanical planarization (CMP) process; and
- forming an interconnect structure within the insulating layer and electrically coupled to the extension pad.
18. The method of claim 17, wherein forming the extension pad comprises:
- forming an extension pad opening in the substrate;
- depositing a metal layer in the extension pad opening; and
- removing a portion of the metal layer.
19. The method of claim 17, wherein forming the polysilicon pillar comprises:
- patterning a polysilicon pillar opening by a photolithography process; and
- forming the polysilicon pillar in the polysilicon pillar opening.
20. The method of claim 17, wherein forming the polysilicon pillar comprises:
- depositing a polysilicon layer on the extension pad; and
- removing a portion of the polysilicon layer by an etching process.
Type: Application
Filed: May 10, 2022
Publication Date: Nov 16, 2023
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsinchu City)
Inventors: Y.C. Chang (Kaohsiung City), Yen-Ting Chiang (Tainan City), Shyh-Fann Ting (Tainan City), Jen-Cheng Liu (Hsinchu City)
Application Number: 17/740,544