Patents by Inventor Jen Chieh Kao
Jen Chieh Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250038136Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: ApplicationFiled: October 15, 2024Publication date: January 30, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
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Publication number: 20240429115Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.Type: ApplicationFiled: September 10, 2024Publication date: December 26, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
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Patent number: 12119312Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: GrantFiled: July 18, 2023Date of Patent: October 15, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
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Patent number: 12087652Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.Type: GrantFiled: August 9, 2022Date of Patent: September 10, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
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Publication number: 20240249988Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a substrate, an electronic component, an intermediate structure and a protective layer. The electronic component is disposed over the substrate. The intermediate structure is disposed over the substrate and comprises an interposer and a conductive element on the interposer. The protective layer is disposed over the substrate and has an upper surface covering the electronic component and being substantially level with an upper surface of the conductive element.Type: ApplicationFiled: January 19, 2023Publication date: July 25, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yu-Chang CHEN, Wei-Tung CHANG, Jen-Chieh KAO
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Publication number: 20240145357Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Lin YEH, Jen-Chieh KAO
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Publication number: 20240126327Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
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Patent number: 11862544Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.Type: GrantFiled: April 23, 2021Date of Patent: January 2, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang-Lin Yeh, Jen-Chieh Kao
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Publication number: 20230361060Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
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Patent number: 11705412Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: GrantFiled: June 14, 2021Date of Patent: July 18, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
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Publication number: 20230026633Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shiu-Fang YEN, Chang-Lin YEH, Jen-Chieh KAO
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Publication number: 20220384289Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
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Publication number: 20220344246Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Lin YEH, Jen-Chieh KAO
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Patent number: 11462455Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.Type: GrantFiled: January 30, 2019Date of Patent: October 4, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shiu-Fang Yen, Chang-Lin Yeh, Jen-Chieh Kao
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Patent number: 11410899Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.Type: GrantFiled: January 23, 2020Date of Patent: August 9, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
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Publication number: 20210305181Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: ApplicationFiled: June 14, 2021Publication date: September 30, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
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Patent number: 11037891Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.Type: GrantFiled: June 26, 2019Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
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Patent number: 10991656Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.Type: GrantFiled: June 19, 2019Date of Patent: April 27, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chang-Lin Yeh, Jen-Chieh Kao
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Patent number: 10950530Abstract: A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate.Type: GrantFiled: May 17, 2019Date of Patent: March 16, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Nan Lin, Jen-Chieh Kao
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Publication number: 20200402911Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.Type: ApplicationFiled: June 19, 2019Publication date: December 24, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chang-Lin YEH, Jen-Chieh KAO