Patents by Inventor Jen Chieh Kao

Jen Chieh Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145357
    Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Patent number: 11862544
    Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: January 2, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Jen-Chieh Kao
  • Publication number: 20230361060
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
  • Patent number: 11705412
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: July 18, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
  • Publication number: 20230026633
    Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.
    Type: Application
    Filed: October 4, 2022
    Publication date: January 26, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shiu-Fang YEN, Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20220384289
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20220344246
    Abstract: The present disclosure provides an electronic assembly including a semiconductor device package. The semiconductor device package includes a first package and a conductive element. The first package includes an electronic component and a protection layer covering the electronic component. The conductive element is supported by the protection layer and electrically connected with the electronic component through an electrical contact. A method for manufacturing a semiconductor device package is also provided in the present disclosure.
    Type: Application
    Filed: April 23, 2021
    Publication date: October 27, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO
  • Patent number: 11462455
    Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shiu-Fang Yen, Chang-Lin Yeh, Jen-Chieh Kao
  • Patent number: 11410899
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao
  • Publication number: 20210305181
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
  • Patent number: 11037891
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 15, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
  • Patent number: 10991656
    Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 27, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang-Lin Yeh, Jen-Chieh Kao
  • Patent number: 10950530
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Jen-Chieh Kao
  • Publication number: 20200402911
    Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20200365499
    Abstract: A semiconductor device package includes a first substrate, a second substrate, a first support element, a second support element and an electronic component. The first substrate has a first surface and a second surface opposite to the first surface. The first substrate has a conductive pad adjacent to the first surface of the first substrate. The second substrate is disposed over the first surface of the first substrate. The first support element is disposed between the first substrate and the second substrate. The first support element is disposed adjacent to an edge of the first surface of the first substrate. The second support element is disposed between the first substrate and the second substrate. The second support element is disposed far away from the edge of the first surface of the first substrate. The electronic component is disposed on the second surface of the first substrate.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Nan LIN, Jen-Chieh KAO
  • Publication number: 20200312733
    Abstract: A semiconductor package structure includes a substrate having a first surface and a second surface opposite to the first surface; a first encapsulant disposed on the first surface of the substrate, and defining a cavity having a sidewall, wherein an accommodating space is defined by the sidewall of the cavity of the first encapsulant and the substrate, and the accommodating space has a volume capacity; and a connecting element disposed adjacent to the first surface of the substrate and in the cavity, wherein a volume of the connecting element is substantially equal to the volume capacity of the accommodating space.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chang-Lin YEH, Jen-Chieh KAO, Sheng-Yu CHEN, Yu-Chang CHEN, Yu-Chang CHEN
  • Publication number: 20200161200
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yi CHEN, Chang-Lin YEH, Jen-Chieh KAO
  • Publication number: 20200098709
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Application
    Filed: June 26, 2019
    Publication date: March 26, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Nan LIN, Wei-Tung CHANG, Jen-Chieh KAO, Huei-Shyong CHO
  • Patent number: 10580713
    Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 3, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yi Chen, Chang-Lin Yeh, Jen-Chieh Kao