Abstract: A chip packaging process is provided. First, a matrix package substrate having a carrying surface with a plurality of scribe lines thereon is provided. The scribe lines divide the package substrate into a plurality of package substrate units. Then, a sealant is formed on each scribe line. A chip is disposed on each package substrate unit. Furthermore, the chip is electrically connected to a corresponding package substrate unit. Thereafter, a transparent cover is disposed over the matrix package substrate. The transparent cover and the matrix package substrate are connected via the sealant. After that, a trimming process along the scribe lines is performed to cut the transparent cover, the matrix package substrate and the sealant.

Abstract: An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

Abstract: A substrate strip for a transparent package has a top surface, a bottom surface and an injection region through the top and bottom surface. The top surface includes a plurality of package regions and a plurality of runner regions. The injection region is disposed between the package regions and is coupled to the runner regions. The injection region has a sidewall with a releasing layer for preventing the residual of clear compound from remaining at the injection region of the substrate strip.

Abstract: A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

Abstract: A wafer-level package includes a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.

Abstract: A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Abstract: The present invention relates to a package structure for a microsystem, comprising a substrate, a chip, an adhesive structure, a carrying substrate, a micro-mechanism, a plurality of wires, an annular body and a transparent plate. The chip is placed on the substrate. The annular adhesive structure having an opening is placed on the chip. The carrying substrate is placed on the adhesive structure, thus forming an interspace between the chip, the adhesive structure and the carrying substrate. The pressure inside the interspace can be balanced with the pressure outside the interspace through the opening. The micro-mechanism is disposed on the carrying substrate. The annular body is formed on the substrate and the transparent plate is attached on the annular body, thus forming a closed chamber between the substrate, the annular body and the transparent plate. The chip, the micro-mechanism, the adhesive structure, the carrying substrate and the wires are disposed within the closed chamber.

Abstract: The present invention relates to a package structure for a microsystem, comprising a substrate, a chip, an adhesive structure, a carrying substrate, a micro-mechanism, a plurality of wires, an annular body and a transparent plate. The chip is placed on the substrate. The annular adhesive structure having an opening is placed on the chip. The carrying substrate is placed on the adhesive structure, thus forming an interspace between the chip, the adhesive structure and the carrying substrate. The pressure inside the interspace can be balanced with the pressure outside the interspace through the opening. The micro-mechanism is disposed on the carrying substrate. The annular body is formed on the substrate and the transparent plate is attached on the annular body, thus forming a closed chamber between the substrate, the annular body and the transparent plate. The chip, the micro-mechanism, the adhesive structure, the carrying substrate and the wires are disposed within the closed chamber.

Abstract: A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip.

Abstract: An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

Abstract: An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.

Abstract: An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.

Abstract: A Liquid crystal display device comprises a base chip, a transparent substrate, a bump ring, and liquid crystal material. The base chip has a plurality of pixel electrodes, a bonding pad ring surrounding the pixel electrodes and a plurality of bonding pads positioned outside the bonding pad ring, electrically connected to the pixel electrodes and adapted being electrically connected to an external circuit. The transparent substrate has a bonding pad ring corresponding to the bonding pad ring of the base chip. The bump ring is disposed between the bonding pad ring of the base chip and the bonding pad ring of the transparent substrate for bonding the base chip and the transparent substrate so as to form a hermetical cavity. The liquid material is filled within the hermetical cavity.

Abstract: A multichip wafer-level package comprises a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding pad ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding pad ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding pad ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding pad ring corresponding to the first bonding pad ring of the first chip.

Abstract: A wafer-level package with bump comprises a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.

Abstract: A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Abstract: An optical integrated circuit element package comprises a lead frame, a chip, a wall, and a transparent cover. The lead frame has a plurality of leads substantially coplanar and defining a central region, and a die pad is disposed on the central region. The chip is disposed on the die pad and has an optical integrated circuit element and a plurality of pads which are electrically connected to the plurality of leads by a plurality of bonding wires. The height of the wall is higher than the chip and the plurality of bonding wires, and the wall has an extending portion hermetically extending between the die pad and the plurality of leads. The extending portion is substantially coplanar with the leads, and the plurality of leads are exposed out of the lower surface of the extending portion. The transparent cover hermetically covers the wall.