Abstract: A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: A semiconductor package device includes: (1) a substrate having a first surface; (2) a permeable element including a first portion disposed on the first surface of the substrate, a second portion protruding from the first portion, and a third portion disposed on the second portion and contacting the second portion of the permeable element; (3) a first electrical element disposed on the substrate and surrounded by the second portion of the permeable element; and (4) a coil disposed on the substrate and surrounding the second portion of the permeable element.

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

Abstract: A semiconductor package device includes a substrate, a first package body, a permeable element and a coil. The substrate includes a first surface. The first package body encapsulates the first surface of the substrate. The permeable element includes a first portion disposed on the first surface of the substrate and a second portion disposed on the package body. The coil is within the first package body.

Abstract: A semiconductor package device includes a first substrate, a second substrate and a first spacer. The first substrate includes a first divided pad. The second substrate includes a second divided pad disposed above the first divided pad. The first spacer is disposed between the first divided pad and the second divided pad. The first spacer is in contact with the first divided pad and the second divided pad.

Abstract: A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

Abstract: A matrix package substrate molding process is provided. First, a matrix package substrate with a plurality of package units for disposing chips on the package units is provided. Next, an encapsulation mold is disposed on each of the package units. The mold has a plurality of mold cavities arranged as branches to correspondingly accommodate a chip. When the encapsulation is filled into the mold and flows into the cavities by branch, the chips on the branch are covered by the encapsulation. After curing the encapsulation, the mold is lifted off to complete the package operation. Accordingly, the processing time and cost are saved.

Abstract: A chip packaging process is provided. First, a matrix package substrate having a carrying surface with a plurality of scribe lines thereon is provided. The scribe lines divide the package substrate into a plurality of package substrate units. Then, a sealant is formed on each scribe line. A chip is disposed on each package substrate unit. Furthermore, the chip is electrically connected to a corresponding package substrate unit. Thereafter, a transparent cover is disposed over the matrix package substrate. The transparent cover and the matrix package substrate are connected via the sealant. After that, a trimming process along the scribe lines is performed to cut the transparent cover, the matrix package substrate and the sealant.

Abstract: An optical component package includes a substrate, an optical component, a plurality of spacers, a plurality of wires, and a transparent molding compound. The optical component is disposed on the substrate, and the surface of the optical component located away from the substrate is used to receive an optical signal. The spacers are disposed between the substrate and optical component. The wires electrically connect the optical component to the substrate. The transparent molding compound encapsulates the optical component. In this case, the diameter of each of the spacers is equal to the thickness of the transparent molding compound minus the thickness of the optical component minus the distance between where the optical signal enters the transparent molding compound and where the optical signal is received by the optical component. Furthermore, this invention also discloses a packaging method for the optical component package.

Abstract: A substrate strip for a transparent package has a top surface, a bottom surface and an injection region through the top and bottom surface. The top surface includes a plurality of package regions and a plurality of runner regions. The injection region is disposed between the package regions and is coupled to the runner regions. The injection region has a sidewall with a releasing layer for preventing the residual of clear compound from remaining at the injection region of the substrate strip.

Abstract: A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

Abstract: A wafer-level package includes a first chip, a second chip and a bump ring. The first chip has a semiconductor micro device, a bonding pad ring surrounding the semiconductor micro device, and a plurality of bonding pads disposed outside the bonding pad ring and electrically connected to the semiconductor micro device for electrically connecting to an external circuit. The second chip has a bonding pad ring corresponding to the bonding pad ring of the first chip. The bump ring is disposed between the bonding pad ring of the first chip and the bonding pad ring of the second chip for bonding the first and the second chips so as to form a hermetical cavity.