Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

Abstract: A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a first guiding assembly. The first movable portion is used for connecting to a first optical element driving mechanism. The first optical element driving mechanism has a main axis that extends in a first direction. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The first guiding assembly is used for guiding the movement of the fixed portion relative to the fixed portion.

Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

Abstract: A packaging substrate assembly for fabricating a packaged module can include a packaging substrate having a surface, and an array of conductive pads implemented on the surface. The assembly can further include a conductive post formed over each conductive pad, with the conductive post including a first portion having a lateral dimension formed over the conductive pad and a second portion having a lateral dimension formed over the first portion. In some embodiments, the lateral dimension of the first portion is less than the lateral dimension of the second portion. In some embodiments, a dielectric layer can be implemented over the surface to cover the conductive pads and surround the first portion of each conductive post.

Abstract: A conductive via layer is deposited on a bottom electrode, then patterned and trimmed to form a sub 20 nm conductive via on the bottom electrode. The conductive via is encapsulated with a first dielectric layer, which is planarized to expose a top surface of the conductive via. A MTJ stack is deposited on the encapsulated conductive via wherein the MTJ stack comprises at least a pinned layer, a barrier layer, and a free layer. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 30 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layer but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Abstract: A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.

Abstract: A transistor device and method of making the same are disclosed. The transistor device includes one or more air gaps in one or more sidewall spacers. The one or more air gaps may be located adjacent the gate and/or above the source or drain regions of the device. Various embodiments may include different combinations of air gaps formed in one or both sidewall spacers. Various embodiments may include air gaps formed in one or both sidewall spacers adjacent to the gate and/or above the source or drain regions of the device. The formation of the air gaps may reduce unwanted parasitic and/or fringing capacitance.

Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.

Abstract: A physiological signal measurement device is disclosed. In some implementations, the physiological signal measurement device includes a fixing element, a rack, a first sensor, and a second sensor. The fixing element is configured to be fixed on a limb of a user. The rack is configured to engage the fixing element and includes a first end and a second end distal to the first end. The first sensor is disposed on the first end of the rack. The sensor is disposed on the second end of the rack. The first end of the rack has a first stiffness, the second end of the rack has a second stiffness, and the first stiffness is higher than the second stiffness.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism is disposed on an electronic apparatus. The optical element driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, a circuit assembly, and a first position sensing assembly. The first movable portion is used for connecting to a first optical element. The first optical element is used for corresponding to light. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The circuit assembly is used for electrically connected to the electronic apparatus. The first position sensing assembly is used for detecting the movement of the first movable portion relative to the fixed portion.

Abstract: A system and a method for drone docking are provided. The method includes: setting a moving platform on a vehicle; obtaining, by the moving platform, current environmental data and historical environmental data corresponding to the moving platform; generating, by the moving platform, a recommended flight parameter according to the current environmental data and the historical environmental data, and transmitting the recommended flight parameter to a drone; and adjusting, by the drone, a flight parameter of the drone according to the recommended flight parameter to dock on the moving platform.

Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A stack of MTJ layers is provided on a bottom electrode. A top electrode is provided on the MTJ stack. The top electrode is patterned. Thereafter, the MTJ stack not covered by the patterned top electrode is oxidized or nitridized. Then, the MTJ stack is patterned to form a MTJ device wherein any sidewall re-deposition formed on sidewalls of the MTJ device is non-conductive and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode.