Abstract: An optical element driving mechanism is provided, which includes a fixed portion, a first movable portion, and a driving assembly. The first movable portion is used for connecting to a first optical element. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion.

Abstract: An optical subassembly for switchably focusing or redirecting a light beam may include a polarization element having a polarization-selective beam redirection/focusing property, a first switchable polarization rotator upstream of the polarization element, and a second switchable polarization rotator downstream of the polarization element. A polarizer may be provided immediately downstream of the second switchable polarization rotator. The first and second switchable polarization rotators may be operated in counterphase, so as to mutually offset dependence of angle and wavelength characteristics of the polarization rotators on the switching state of the polarization rotators.

Abstract: A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A construction combination includes a construction member, and an acoustic absorbing device engaged in the construction member for absorbing acoustic sounds. The acoustic absorbing device includes a housing engaged in the construction member, and a casing engaged in the housing. The housing includes one or more couplers, and the casing includes one or more connectors for engaging with the couplers and for anchoring the casing in the housing. A sound absorbing member is engaged in the casing, and the sound absorbing member includes an anchor for engaging with the casing and for anchoring the sound absorbing member in the casing.

Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.

Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.

Abstract: An optical system is provided, including a movable part, a fixed part, a first sensor, a second sensor, and a control unit, wherein an optical element is disposed on the movable part. The first and second sensors detect the movement of the movable part relative to the fixed part in a first dimension and a second dimension, and thus they respectively generate a first sensing value and a second sensing value. The control unit generates an error value according to the first sensing value and an error curve, and then calibrates the second sensing value according to the error value.

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method is disclosed for forming a SiON encapsulation layer on a magnetic tunnel junction (MTJ) sidewall that minimizes attack on the MTJ sidewall during the PECVD or subsequent processes. The PECVD method provides a higher magnetoresistive ratio for the MTJ than conventional methods after a 400° C. anneal. In one embodiment, the SiON encapsulation layer is deposited using a N2O:silane flow rate ratio of at least 1:1 but less than 15:1. A N2O plasma treatment may be performed immediately following the PECVD to ensure there is no residual silane in the SiON encapsulation layer. In another embodiment, a first (lower) SiON sub-layer has a greater Si content than a second (upper) SiON sub-layer. A second encapsulation layer is formed on the SiON encapsulation layer so that the encapsulation layers completely fill the gaps between adjacent MTJs.

Abstract: An electronic package structure includes an electronic structure, a wiring structure, an electrical contact and a support layer. The wiring structure is located over the electronic structure. The electrical contact connects the wiring structure and the electronic structure. The support layer is disposed around the electrical contact and has a surface facing the electrical contact. The surface includes at least one inflection point in a cross-sectional view.

Abstract: An ultra-large height top electrode for MRAM is achieved by employing a novel thin metal/thick dielectric/thick metal hybrid hard mask stack. Etching parameters are chosen to etch the dielectric quickly but to have an extremely low etch rate on the metals above and underneath. Because of the protection of the large thickness of the dielectric layer, the ultra-large height metal hard mask is etched with high integrity, eventually making a large height top electrode possible.

Abstract: An RRAM includes a bottom electrode, a resistive switching layer, a top electrode and a cap layer stacked from bottom to top. The cap layer includes a top surface. A first spacer contacts a first sidewall of the bottom electrode, and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and contacts a third spacer of the top electrode. A thickness of the first spacer is greater of a thickness of the second spacer. The first spacer and the second spacer do not cover the topmost surface of the cap layer.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may determine to perform garbage collection on a superblock. During the garbage collection process, the controller will typically move the superblock into an erase pool for erasing the superblock. However, aspects of the disclosure are directed to a method of measuring a raw bit error rate (RBER) of the superblock prior to erasure. The measured RBER may be used to estimate a data retention time of the storage device and provide the customer with an early warning notification if a health metric of the storage devices reaches a threshold retention time.

Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.

Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.

Abstract: A semiconductor device including a magnetic random access memory (MRAM) cell includes first and second magnetic random access memory (MRAM) cell structures disposed over a substrate. Each of the first and second MRAM cell structures includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, and a top electrode. The semiconductor device further includes a first insulating cover layer covering sidewalls of each of the first and second MRAM cell structures, and a second insulating cover layer disposed over the first insulating cover layer. The semiconductor device further includes a bottom dielectric layer filling a space between the first and second MRAM cell structures, and an upper dielectric layer disposed over the bottom dielectric layer. Each of the first insulating cover layer and the second insulating cover layer is discontinuous between the first MRAM cell structure and the second MRAM cell structure.

Abstract: A semiconductor structure includes a semiconductor substrate, an interconnection structure, a color filter, and a first isolation structure. The semiconductor substrate includes a first surface and a second surface opposite to the first surface. The interconnection structure is disposed over the first surface, and the color filter is disposed over the second surface. The first isolation structure includes a bottom portion, an upper portion and a diffusion barrier layer surrounding a sidewall of the upper portion. A top surface of the upper portion of the first isolation structure extends into and is in contact with a dielectric layer of the interconnection structure.

Abstract: Devices and methods of manufacture and use of a fiber bundle is presented. In embodiments the fiber bundle comprises a substrate material and optical fiber openings that extend from a first side of the substrate material to a second side of the substrate material, wherein the optical fiber openings at the first side of the substrate material are shifted either horizontally or vertically from the second side of the substrate material.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a dam is surrounding an electronic component on a carrier structure, the electronic component is encapsulated by a thermal conduction layer, and the electronic component, the dam and the thermal conduction layer are covered by a heat sink, such that the dam strongly supports the heat sink to effectively disperse the thermal stress, so as to effectively control the warpage of the heat sink to prevent the problem of delamination from occurring between the heat sink and the thermal conduction layer.