Abstract: A method for manufacturing an electronic device is provided. In the method for manufacturing an electronic device, a substrate is provided, a device layer is disposed on the substrate, and a photoresist layer is disposed on the device layer. Next, a photo mask is disposed on the photoresist layer, and a light source is used to firstly illuminate the photo mask to form a first exposure region. After that, a relative movement is made between the substrate and the photo mask, and the light source is used to secondly illuminate the photo mask to form a second exposure region, wherein the first exposure region partially overlaps the second exposure region. Afterwards, a pattern is developed on the substrate, the device layer is etched using a patterned photoresist layer as an etching mask, and then the patterned photoresist layer is removed.

Abstract: An optical module is provided. The optical module includes an immovable part, a movable part, and a connecting unit. The movable part is movable relative to the immovable part. The movable part is connected to an optical assembly. The movable part is movably connected to the immovable part via the connecting unit.

Abstract: An electronic package and method of manufacture are provided. The method includes providing an electronic module. The electronic module has a group of electrically conductive nodes. The method includes providing a substrate panel, in which a plurality of electrically conductive contact pads are arranged on a surface of the substrate panel, a predetermined one of the plurality of electrically conductive contact pads associated with the group of the electrically conductive nodes. The method includes defining a solder masking arrangement extending over a part of the surface of the substrate panel to overlie the predetermined electrically conductive contact pad such that the masking arrangement at least partially defines a group of spatially distinct fusion areas each associated with a corresponding one of the group of the electrically conductive nodes.

Abstract: A magnetic tunneling junction (MTJ) structure comprises a pinned layer on a bottom electrode. a barrier layer on the pinned layer, wherein a second metal re-deposition layer is on sidewalls of the barrier layer and the pinned layer, a free layer on the barrier layer wherein the free layer has a first width smaller than a second width of the pinned layer, a top electrode on the free layer having a same first width as the free layer wherein a first metal re-deposition layer is on sidewalls of the free layer and top electrode, and dielectric spacers on sidewalls of the free layer and top electrode covering the first metal re-deposition layer wherein the free layer and the top electrode together with the dielectric spacers have a same the second width as the pinned layer wherein the dielectric spacers prevent shorting between the first and second metal re-deposition layers.

Abstract: An optical module is provided. The optical module includes an immovable part, a movable part, and a connecting unit. The movable part is movable relative to the immovable part within a movement range. The movable part is connected to an optical assembly. The movable part is movably connected to the immovable part via the connecting unit.

Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1<RA2 and RACAP<RA2 is achieved when TB1 and the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB2, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Abstract: An integrated circuit layout includes an upper active region comprising a first edge and a second edge extending along a first direction and respectively adjacent to an upper cell boundary by a distance D3 and a distance D4. A first gate line is disposed on the upper active region, extends along a second direction, and protrudes from the first edge by a length L3. A second gate line is disposed on the upper active region, extends along the second direction, and protrudes from the second edge by a length L4. Two dummy gate lines respectively extend along the second direction and are disposed at two sides of the upper active region and away from the upper cell boundary by a distance S. The first direction and the second direction are perpendicular. The distances D3, D4, S and the lengths L3 and L4 have the relationships: L3?D3?S, L4?D4?S, and D3?D4.

Abstract: A method includes connecting a photonic package to a substrate, wherein the photonic package includes a waveguide and an edge coupler that is optically coupled to the waveguide; connecting a semiconductor device to the substrate adjacent the photonic package; depositing a first protection material on a first sidewall of the photonic package that is adjacent the edge coupler; encapsulating the photonic package and the semiconductor device with an encapsulant; performing a first sawing process through the encapsulant and the substrate, wherein the first sawing process exposes the first protection material; and removing the first protection material to expose the first sidewall of the photonic package.

Abstract: A semiconductor device package includes a substrate having a surface, a conductive element disposed on the surface of the substrate, and an encapsulant disposed on the surface of the substrate and covering the conductive element. The conductive element has an upper surface facing away from the substrate and exposed from the encapsulant. Further, a roughness of the upper surface of the conductive element is greater than a roughness of a side surface of the conductive element.

Abstract: A light-emitting diode (“LED”) package includes a package housing defining a space. The LED package includes a first LED disposed with the space defined by the package housing, and configured to emit a first light having a blue wavelength range. The blue wavelength range has a peak wavelength ranging from about 440 nm to about 480 nm. The LED package includes a second LED disposed within the space, and configured to emit a second light having a red wavelength range. The red wavelength range has a peak wavelength ranging from about 610 nm to about 680 nm. The LED package includes a phosphor filler filling the space and configured to absorb a portion of the first light to emit a third light having a green wavelength range. The green wavelength range has a peak wavelength ranging from about 510 nm to about 570 nm.

Abstract: An improved switching power converting apparatus (10) includes a power converting circuit (102), a sampling circuit (104), a signal gain adjustment circuit (106), a frequency limiting circuit (108) and a pulse width modulation controller (110). The sampling circuit (104) is configured to detect the power converting circuit (102) to obtain a sampled signal (Vs) and transmit the sampled signal (Vs) to the signal gain adjustment circuit (106). The signal gain adjustment circuit (106) is configured to adjust the sampled signal (Vs) to obtain a control signal (Vcon) and transmit the control signal (Vcon) to the frequency limiting circuit (108). The pulse width modulation controller (110) is configured to control an operating frequency of the pulse width modulation controller (110) based on the control signal (Vcon).

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: An integrated chip including a reference magnetic layer and a barrier layer over the reference magnetic layer. A first free magnetic layer is over the barrier layer. A second free magnetic layer is over the first free magnetic layer. A spacer layer is between the first free magnetic layer and the second free magnetic layer. The spacer layer includes magnesium and a transition metal. An atomic ratio of the magnesium to the transition metal ranges from 15% to 80%.

Abstract: A resistive memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; and a memory stack structure disposed on the conductive via and the dielectric layer. The memory stack structure includes a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer. The top electrode layer includes at least two physically separated sub-electrode portions.

Abstract: A method for creating work substantiation material and a work-substantiation system are provided. In the method for creating work substantiation material performed in the system, the serving system firstly receives a digital image after a digitization process. After retrieving image data, a work substantiation data can be computed, and a creator substantiation data with respect to a creator or related information can also be computed. After combining the work substantiation data and the creator substantiation data, an amalgamated substantiation data with respect to the work is formed. The amalgamated substantiation data can be incorporated, or appended onto a tangible work; or can be integrated into a digital work through a specific method.

Abstract: The present invention discloses an automatic signal deployer, a signal deployment system, an automatic signal path deployment method, and a behavior control signal generation method of a deployment agent. The signal deployment system includes an automatic signal deployer, a deployment agent and a base station. The deployment agent receives signal quality data, generates a behavior control signal according to the signal quality data, and sends out the behavior control signal to the automatic signal deployer. The automatic signal deployer receives the behavior control signal and a source signal coming from the base station, performs deployment according to the behavior control signal, whereby the automatic signal deployer can transmit the source signal toward a signal path allocation direction and complete automatic deployment of signal paths.

Abstract: A cover for an underground enclosure may include an upper surface comprising a pattern of bosses, a first slot and a second slot disposed on the upper surface, a lower surface opposite the upper surface. A first reinforcement member may be coupled to the lower surface. The first slot may extend into the first reinforcement member, and a second reinforcement member may be coupled to the lower surface and aligned with the first reinforcement member. The second slot may extend into the second reinforcement member. The cover may be configured to be lifted by the first slot and the second slot.

Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.

Abstract: A graph-based natural language optimization method and an electronic apparatus are provided. The method is adapted for an electronic apparatus with a processor. In the method, an input sentence submitted by a user is received, and multiple domain-related entities are extracted from the input sentence. The domain-related entities are input to a graph database to analyze a connection relationship between the domain-related entities, and filling data is obtained from the graph database based on the connection relationship. The input sentence and the filling data are integrated via a natural language processing technology to generate an optimized natural language sentence.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.