Abstract: The present disclosure provides a multi-manifold embedding learning method, which includes steps as follows. The ID training data are used to train the multi-manifold embedding learning model, and then the parameters of the multi-manifold embedding learning model are frozen to obtain the trained multi-manifold embedding learning model; the test data are fed to the trained multi-manifold embedding learning model, so as to use a threshold to distinguish out-of-distribution samples from ID samples.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Abstract: A device includes a detector transistor, a sensing pad, a first conductive ring, a second conductive ring, a first transistor, and a second transistor. The sensing pad is over the detector transistor. The first conductive ring is over the sending pad. The second conductive ring is over the first conductive ring. The first transistor has a source/drain region electrically coupled to the first conductive ring. The second transistor has a source/drain region electrically coupled to the second conductive ring.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a plurality of base regions formed over the collector region, a plurality of emitter regions formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, a plurality of base conductive layers formed over the collector region and on opposite sides of the base regions, a plurality of sidewall dielectric layers formed on top surfaces of the base conductive layers and disposed vertically between the base conductive layers and upper portions of the emitter regions, and a plurality of base contacts formed on the base conductive layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.

Abstract: A method for calculating optical aerial images. The method includes following steps. A first pattern distribution in a spatial domain is multiplied by a scaling constant to scale the first pattern distribution to generate a second pattern distribution. A fast Fourier transform is performed on the second pattern distribution to generate a first spatial frequency spectrum distribution in a spatial frequency domain. The first spatial frequency spectrum distribution is multiplied by a pupil function to generate a second spatial frequency spectrum distribution. An inverse fast Fourier transform is performed on the second spatial frequency spectrum distribution to generate a first diffraction image distribution in the spatial domain. The first diffraction image distribution is divided by a scaling constant to scale the first diffraction image distribution to generate a second diffraction image distribution.

Abstract: A device includes a detector, a sensing pad, a ring structure, a control circuit, a first transistor, and a second transistor. The sensing pad is electrically connected to the detector. The ring structure is over the sensing pad and includes an upper conductive ring and a lower conductive ring between the upper conductive ring and the sensing pad. The first transistor interconnects the upper conductive ring and the control circuit. The second transistor interconnects the lower conductive ring and the control circuit.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a supporting structure having a supporting body is disposed on a carrying structure and is in contact with or in proximity to an electronic component, and a barrier structure is disposed on the supporting body, such that the electronic component is exposed from an opening of the barrier structure. Furthermore, a thermal conduction layer is formed on the electronic component exposed from the opening of the barrier structure, and the barrier structure blocks or surrounds the thermal conduction layer on the electronic component, thereby preventing the thermal conduction layer from overflowing.

Abstract: Bipolar junction transistor (BJT) structures are provided. A BJT structure includes a semiconductor substrate, a collector region formed in the semiconductor substrate, a base region formed over the collector region, an emitter region formed over the collector region, a ring-shaped shallow trench isolation (STI) region formed in the collector region, and a base dielectric layer formed over the collector region and on opposite sides of the base region. The base dielectric layer is surrounded by an inner side wall of the ring-shaped STI region.

Abstract: A device includes an active region, an isolation structure, a gate structure, an interlayer dielectric (ILD) layer, a reading contact, and a sensing contact. The isolation structure laterally surrounds the active region. The gate structure is across the active region. The ILD layer laterally surrounds the gate structure. The reading contact is in contact with the isolation structure and is separated from the gate structure by a first portion of the ILD layer. The sensing contact is in contact with the isolation structure and is separated from the gate structure by a second portion of the ILD layer.

Abstract: A method for inspecting particles is suitable for inspecting particles on a substrate. The method for inspecting the particles includes the following. The substrate is disposed on a stage. An inspection radiation is provided to irradiate on the substrate, in which the inspection radiation is suitable for exciting the particles on the substrate to emit a secondary radiation. Also, the secondary radiation is detected to confirm whether the particles exist on the substrate and positions of the particles are detected.

Abstract: A vertical-cavity surface-emitting laser array includes a substrate. The VCSEL array also includes an active layer formed between a lower mirror and an upper mirror. The VCSEL array also includes a contact layer formed between the active layer and the substrate. The VCSEL array also includes an isolation trench between the first VCSEL and the second VCSEL of the VCSEL array. The isolation trench extending through the contact layer is filled with a filler.

Abstract: A system and method for determining an activity coefficient (?i) for an electrolyte mixture by providing one or more processors, a. memory communicably coupled to the one or more processors and an output device communicably coupled to the one or more processors, calculating, using the one or more processors, the activity coefficient (?i) for the electrolyte mixture based, on association interactions between any species that associate, long-range interactions between ions, and short-range interactions between any species, providing the activity coefficient (?i) for the electrolyte mixture to the output device, and developing a chemical process or a product using the activity coefficient (?i) for the electrolyte mixture.

Abstract: A semiconductor device includes a sensing element including a sensing electrode and a filter covering the sensing electrode. The filter includes a first work function layer and a second work function layer. The first work function layer is over the sensing electrode. The second work function layer is over the first work function layer. A work function value of the second work function layer is greater than a work function value of the first work function layer, and an atomic percentage of metal in the second work function layer is greater than an atomic percentage of metal in the first work function layer.

Abstract: A device in a chamber is provided. The device comprises at least one die. The at least one die comprise a first voltage generator, a dielectric layer and a first voltage regulator circuit. The first voltage generator is charged to have a first induced voltage by induced charges generated in response to a first voltage of a first electrode of a chuck in the chamber. The dielectric layer surrounds the first voltage generator to isolate the first voltage generator from the first electrode. The first voltage regulator circuit is coupled to the first voltage generator to receive the first induced voltage and generates a first power supply voltage according to the first induced voltage for a first circuit in the device.

Abstract: A method for unseen emotion class recognition comprises: receiving, with an emotion recognition model, a speech sample to be tested; calculating, with an encoder, a sample embedding to be tested of the speech sample to be tested; calculating a first distance metric between the sample embedding to be tested and a first registered emotion category representation, and a second distance metric between the sample embedding to be tested and a second registered emotion category representation, wherein the second registered emotion category is not included in a plurality of basic emotion categories; and determining an emotion category of the speech sample to be tested according to the first distance metric and the second distance metric.

Abstract: Methods for fabricating a bipolar junction transistor (BJT) are provided. A method includes forming a collector region, forming base regions over the collector region, and forming emitter regions over the base regions. The method further includes forming base dielectric layers over the collector region and on opposite sides of the base regions, forming base conductive layers over the base dielectric layers and on the opposite sides of the base regions, and forming base contacts over the base conductive layers. The top surface of the collector region is coplanar with bottom surfaces of the base regions and bottom surfaces of the base dielectric layers. The base contacts are divided into a first group of base contacts disposed between the base regions and a second group of base contacts disposed between the base regions and the STI region.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a dam is surrounding an electronic component on a carrier structure, the electronic component is encapsulated by a thermal conduction layer, and the electronic component, the dam and the thermal conduction layer are covered by a heat sink, such that the dam strongly supports the heat sink to effectively disperse the thermal stress, so as to effectively control the warpage of the heat sink to prevent the problem of delamination from occurring between the heat sink and the thermal conduction layer.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an energy sensing film. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The energy sensing film is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the energy sensing film is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a first electrode over a substrate. A first capacitor dielectric layer is over an upper surface of the first electrode. The upper surface of the first electrode laterally extends to opposing outermost sidewalls of the first capacitor dielectric layer. A second electrode is over the first capacitor dielectric layer. The upper surface of the first electrode extends past opposing sides of the second electrode. A second capacitor dielectric layer is over the second electrode. A third electrode has a lower surface directly over an upper surface of the second capacitor dielectric layer and completely confined over the second electrode.