Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.

Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: A micro detector includes a substrate, a fin structure, a floating gate, a sensing gate, a reading gate and an antenna layer. The fin structure is located on the substrate. The floating gate is located on the substrate, and the floating gate is vertically and crossly arranged with the fin structure. The sensing gate is located at one side of the fin structure. The reading gate is located at the other side of the fin structure. The antenna layer is located on the sensing gate and is connected with the sensing gate. An induced charge is generated when the antenna layer is contacted with an external energy source, and the induced charge is stored in the floating gate.

Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.

Abstract: A semiconductor device structure and the formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or both of a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltage coefficient is negative.

Abstract: The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: A package stacked structure and a method for fabricating the same are provided. The method includes providing a wiring structure disposed with a carrier and a carrier structure provided with an electronic component. The wiring structure is bonded to the carrier structure via a plurality of conductive elements. An encapsulating layer is formed between the wiring structure and the carrier structure and encapsulates the conductive elements and the electronic component. The carrier is then removed. With the arrangement of the carrier, the structural strength of the wiring structure is improved, and warpage of the wiring structure is prevented before stacking the wiring structure onto the carrier structure.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: Immersion lithography system and method using a sealed wafer bottom are described. One embodiment is an immersion lithography apparatus comprising a lens assembly comprising an imaging lens and a wafer stage for retaining a wafer beneath the lens assembly, the wafer stage comprising a seal ring disposed on a seal ring frame along a top edge of the wafer retained on the wafer stage, the seal ring for sealing a gap between an edge of the wafer and the wafer stage. The embodiment further includes a fluid tank for retaining immersion fluid, the fluid tank situated with respect to the wafer stage for enabling full immersion of the wafer retained on the wafer stage in the immersion fluid and a cover disposed over at least a portion of the fluid tank for providing a temperature-controlled, fluid-rich environment within the fluid tank.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout, which has a plurality of main features and a plurality of space blocks. The IC method also includes calculating an optimized block dummy density ratio r0 to optimize a uniformity of pattern density (UPD), determining a target block dummy density ratio R, determining size, pitch and type of a non-printable dummy feature, generating a pattern for dummy features and adding the dummy features in the IC design layout.

Abstract: The present disclosure provides one embodiment of an IC method. First pattern densities (PDs) of a plurality of templates of an IC design layout are received. Then a high PD outlier template and a low PD outlier template from the plurality of templates are identified. The high PD outlier template is split into multiple subsets of template and each subset of template carries a portion of PD of the high PD outlier template. A PD uniformity (PDU) optimization is performed to the low PD outlier template and multiple individual exposure processes are applied by using respective subset of templates.

Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.