Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.

Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.

Abstract: A semiconductor structure, includes a logic die, a memory die stack bonded to the logic die by a first oxide bond, and including a first pair of memory dies bonded together by a first direct bond, and a first through silicon via (TSV) in the logic die and extending across the first oxide bond and electrically connecting the logic die to the first pair of memory dies.

Abstract: A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface.

Abstract: A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

Abstract: An antenna device includes a radio frequency (RF) die, a first dielectric layer, a feeding line, a ground line, a second dielectric layer, and a radiating element. The first dielectric layer is over the RF die. The feeding line is in the first dielectric layer and is connected to the RF die. The ground line is in the first dielectric layer and is spaced apart from the feeding line. The second dielectric layer covers the first dielectric layer. The radiating element is over the second dielectric layer and is not in physically contact with the feeding line.

Abstract: A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

Abstract: An antenna device includes a package, a radiating element, and a director. The package includes a radio frequency (RF) die and a molding compound in contact with a sidewall of the RF die. The radiating element is in the molding compound and electrically coupled to the RF die. The director is in the molding compound, wherein the radiating element is between the director and the RF die, and a top of the radiating element is substantially coplanar with a top of the director.

Abstract: A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface.

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.

Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.

Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.

Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.

Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: An antenna device includes a package, a radiating element, and a director. The package includes a radio frequency (RF) die and a molding compound in contact with a sidewall of the RF die. The radiating element is in the molding compound and electrically coupled to the RF die. The director is in the molding compound, wherein the radiating element is between the director and the RF die, and a top of the radiating element is substantially coplanar with a top of the director.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.