Abstract: A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface.

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.

Abstract: A manufacturing method of a semiconductor package is provided. The method includes: providing an initial rigid-flexible substrate, wherein the initial rigid-flexible substrate includes rigid structures and a flexible core laterally penetrating through the rigid structures, and further includes a supporting frame connected to the rigid structures; bonding a package structure onto the initial rigid-flexible substrate, wherein the package structure includes semiconductor dies and an encapsulant laterally surrounding the semiconductor dies; and removing the supporting frame.

Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.

Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.

Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.

Abstract: A method includes placing a device die and a pre-formed dielectric block over a first carrier, encapsulating the device die and the pre-formed dielectric block in an encapsulating material, grinding a top side of the encapsulating material to expose the top side of the pre-formed dielectric block, removing the carrier from the encapsulating material, the pre-formed dielectric block, and the device die to reveal a bottom side of the pre-formed dielectric block, and forming a ground panel, a feeding line, and a patch on the encapsulating material. The ground panel, the feeding line, the patch, and the pre-formed dielectric block form a patch antenna.

Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: An antenna device includes a package, a radiating element, and a director. The package includes a radio frequency (RF) die and a molding compound in contact with a sidewall of the RF die. The radiating element is in the molding compound and electrically coupled to the RF die. The director is in the molding compound, wherein the radiating element is between the director and the RF die, and a top of the radiating element is substantially coplanar with a top of the director.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, an insulating layer contacting the second surface of the interconnect structure wherein the insulating layer has a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface, at least one optical chip over the fourth surface of the insulating layer and electrically coupled to the interconnect structure, and a molding compound over the first surface of the interconnect structure.

Abstract: An antenna device includes a package and at least one antenna. The package includes at least one radio frequency (RF) die and a molding compound in contact with at least one sidewall of the RF die. The antenna has at least one conductor at least partially in the molding compound and operatively connected to the RF die.

Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.

Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.

Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.

Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.

Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.

Abstract: An antenna comprises a first layer having a first redistribution layer, a feeding line, a ground connection element, and one or more antenna inputs. The antenna also comprises one or more intermediate layers over the first layer. The antenna further comprises a second layer having a second redistribution layer over the one or more intermediate layers. The antenna additionally comprises one or more through vias arranged to communicatively couple the second redistribution layer and the first redistribution layer. The antenna also comprises a short element. The antenna further comprises one or more radiator antennas within the one or more through vias, the one or more radiator antennas being in communication with the one or more antenna inputs by way of the feeding line.

Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.