Abstract: An integrated circuit for pattern detection including: an arithmetic logic unit coupled to a comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected pattern of a plurality of patterns selected by a first multiplexer, where the first multiplexer is coupled to the comparison circuit; and a register coupled to the comparison circuit for storing at least a partial comparison between an output of the arithmetic logic unit and the selected pattern.

Abstract: A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.

Abstract: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

Abstract: An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.

Abstract: Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.

Abstract: The invention is directed to novel compositions of matter and methods of detecting in situ an immunohistochemical epitope or nucleic acid sequence of interest in a biological sample comprising binding an enzyme-labeled conjugate molecule to the epitope or sequence of interest in the presence of a redox-inactive reductive species and a soluble metal ion, thereby facilitating the reduction of the metal ion to a metal atom at or about the point where the enzyme is anchored. Novel phosphate derivatives of reducing agents are described that when exposed to a phosphatase are activated to their reducing form, thereby reducing metal ions to insoluble metal.

Abstract: Described herein are methods and medical devices used to deliver bioactive agents locally to patients in need of treatment and/or prevention of cardiovascular conditions Local delivery of protease-activated receptor 1 (PAR-1) antagonists are described herein from implantable medical devices including, but not limited to, stents.

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Abstract: Antibody/signal-generating moiety conjugates are disclosed that include an antibody covalently linked to a signal-generating moiety through a heterobifunctional polyalkyleneglycol linker. The disclosed conjugates show exceptional signal-generation in immunohistochemical and in situ hybridization assays on tissue sections and cytology samples. In one embodiment, enzyme-metallographic detection of nucleic acid sequences with hapten-labeled probes can be accomplished using the disclosed conjugates as a primary antibody without amplification.

Abstract: Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Abstract: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

Abstract: Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M?1) and 2(M?1)?1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.

Abstract: Method and apparatus for configuring a programmable logic device to operate at a plurality of clock frequencies comprising configurable programmable self-timed delay circuits and associated configuration software. The configurable IC clock frequencies increase device performance and manufacturing yield.

Abstract: Apparatuses and methods for performing minimally invasive medical procedures are disclosed herein. In one example, an apparatus includes an elongate body that has a deformable distal portion and defines a lumen, the lumen extends through the deformable distal portion. The deformable distal portion has a cutting portion and defines an opening. The elongate body has a first configuration in which the opening is a first size and a second configuration in which the opening is a second size smaller than the first size of the opening. The elongate body in the first configuration is configured to be percutaneously inserted at least partially into a tissue such that at least a portion of the tissue is disposed within the lumen. The elongate body is configured to move to the second configuration when the elongate body reaches a threshold temperature while inserted in the tissue.

Abstract: A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

Abstract: A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.

Abstract: Implantable medical devices having anti-restenotic coatings are disclosed. Specifically, implantable medical devices having coatings of certain NF-kappaB inhibitors, particularly certain dialkyl fumarates, are disclosed. Dimethyl fumarate is a particularly preferred dialkyl fumarate. The anti-restenotic medical devices include stents, catheters, micro-particles, probes and vascular grafts. Intravascular stents are preferred medical devices. The medical devices can be coated using any method known in the art including compounding the dialkyl fumarate with a biocompatible polymer prior to applying the coating. Moreover, medical devices composed entirely of biocompatible polymer-dialkyl fumarate blends are disclosed. Additionally, medical devices having a coating comprising at least one dialkyl fumarate in combination with at least one additional therapeutic agent are also disclosed. Furthermore, related methods of using and making the anti-restenotic implantable devices are also disclosed.

Abstract: Programmable logic devices (PLDs) including self-repairing RAM circuits, and methods of automatically replacing defective columns in RAM arrays. A RAM circuit including redundant columns is tested during the PLD configuration sequence using a built in self test (BIST) procedure. If a defective column is detected, an error flag is stored in an associated volatile memory circuit. After the BIST procedure is complete, the PLD configuration process continues. The presence of the error flag causes the configuration data to bypass the defective column and to be passed directly into a replacement column. The configuration process continues until the remainder of the circuit is configured, including the redundant column. In other embodiments, the BIST procedure is initiated independently from the PLD configuration process. When a defective column is detected, user operation resumes with data being shunted from the defective column to a redundant column in a fashion transparent to the user.

Abstract: Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.