Patents by Inventor Jens Pohl

Jens Pohl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure and method for making same
    Patent number: 8330274
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • Semiconductor device including molding compound layer forms a common plane with the surface of the semiconductor chip
    Patent number: 8330273
    Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Rainer Steiner
  • Structure for electrostatic discharge in embedded wafer level packages
    Patent number: 8309454
    Abstract: A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: November 13, 2012
    Assignee: Intel Mobile Communications GmbH
    Inventors: Markus Brunnbauer, Thorsten Meyer, Stephan Bradl, Ralf Plieninger, Jens Pohl, Klaus Pressel, Recai Sezi
  • SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE
    Publication number: 20120256315
    Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 11, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thorsten Meyer, Markus Brunnbauer, Jens Pohl
  • On-Chip RF Shields with Backside Redistribution Lines
    Publication number: 20120258594
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Semiconductor chip package, semiconductor chip assembly, and method for fabricating a device
    Patent number: 8202763
    Abstract: A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 19, 2012
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Markus Brunnbauer, Jens Pohl
  • High activity growth factor mutants
    Patent number: 8188226
    Abstract: The application relates to novel biosynthetic growth factor mutants, derived from GDF-5, which exhibit improved biological activity. Mutations at positions 453 and 456 of human GDF-5 are disclosed, as well as use of these mutants in therapy of diseases associated with tissue degeneration/destruction.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: May 29, 2012
    Assignee: Biopharm Gesellschaft zur biotechnologischen Entwicklung von Pharmaka mbH
    Inventors: Jens Pohl, Frank Ploeger, Michael Kruse
  • On-chip RF shields with through substrate conductors
    Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • Method of treating diseases or abnormal conditions of periodontal or dental tissues with GDF5
    Patent number: 8163694
    Abstract: The present invention concerns improved osteoinductive materials comprising matrix materials and morphogenetic proteins, wherein depending on the subject matter the proteins may be dimeric or monomeric proteins. The osteoinductive materials according to the present invention have improved properties. The invention further concerns methods for producing the respective improved osteoinductive materials.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: April 24, 2012
    Assignee: Biopharm Gesellschaft zur Biotechnologischen Entwicklung von Pharmaka mbH
    Inventors: Jens Pohl, Rolf Bechtold, Michael Kruse
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120080791
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Semiconductor structure and method for making same
    Patent number: 8148257
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120074574
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Semiconductor device with arrangement of parallel conductor lines being insulated, between and orthogonal to external contact pads
    Patent number: 8080880
    Abstract: A semiconductor device and manufacturing method. One embodiment provides a device including a semiconductor chip. A first conductor line is placed over the semiconductor chip. An external contact pad is placed over the first conductor line. At least a portion of the first conductor line lies within a projection of the external contact pad on the semiconductor chip.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 20, 2011
    Assignee: Infineon Technologies AG
    Inventors: Markus Brunnbauer, Jens Pohl, Thorsten Meyer
  • Semiconductor device including conductive element
    Patent number: 8072071
    Abstract: A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Markus Brunnbauer, Gottfried Beer
  • Semiconductor device
    Patent number: 8071428
    Abstract: A semiconductor device and method. One embodiment provides an encapsulation plate defining a first main surface and a second main surface opposite to the first main surface. The encapsulation plate includes multiple semiconductor chips. An electrically conductive layer is applied to the first and second main surface of the encapsulation plate at the same time.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: December 6, 2011
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Markus Brunnbauer, Irmgard Escher-Poeppel, Thorsten Meyer
  • Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package
    Publication number: 20110291256
    Abstract: A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Inventors: Rainer Steiner, Jens Pohl, Werner Robl, Gottfried Beer
  • Method for producing a module with components stacked one above another
    Patent number: 7993969
    Abstract: The invention relates to a method in which components (101, 102) are provided, movement elements (104) are in each case applied to surfaces of a number of the components (101), and the components (101, 102) are stacked, so that one or a plurality of the movement elements (104) are situated between adjacent components (101, 102) and the components (101, 102) are held in their position by connecting elements (103).
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: August 9, 2011
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Michael Bauer
  • Integrated circuit with re-route layer and stacked die assembly
    Patent number: 7948071
    Abstract: An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: May 24, 2011
    Assignee: Qimonda AG
    Inventors: Jochen Thomas, Peter Weitz, Jurgen Grafe, Harry Hedler, Jens Pohl
  • Reconfigured wafer alignment
    Patent number: 7943423
    Abstract: A method of manufacturing semiconductor device comprises placing multiple chips onto a carrier. An encapsulation material is applied to the multiple chips and the carrier for forming an encapsulation workpiece. The encapsulation workpiece having a first main face facing the carrier and a second main face opposite to the first main face. Further, marking elements are applied to the encapsulation workpiece relative to the multiple chips, the marking elements being detectable on the first main face and on the second main face.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: May 17, 2011
    Assignee: Infineon Technologies AG
    Inventors: Jens Pohl, Edward Fuergut, Markus Brunnbauer, Thorsten Meyer, Peter Strobel, Daniel Porwol, Ulrich Wachter
  • DEVICE FABRICATED USING AN ELECTROPLATING PROCESS
    Publication number: 20110101532
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel