Patents by Inventor Jeon Il LEE
Jeon Il LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129725Abstract: A service identifying and processing method using a wireless terminal message according to an exemplary embodiment of the present invention includes (a) receiving a wireless terminal message by a first entity which is a mobile device; and (b) expressing, by a first agent which is an information processing application program installed on the first entity, entity information of second entity based on the wireless terminal message and service confirmation information related to service provided by the second entity, through an application screen by the first agent.Type: ApplicationFiled: December 23, 2021Publication date: April 18, 2024Applicant: ESTORM CO., LTD.Inventors: Jong Hyun WOO, Tae Il LEE, Il Jin JUNG, Hee Jun SHIN, Hyung Seok JANG, Min Jae SON, Sang Heon BAEK, Seo Bin PARK, Hyo Sang KWON, Mi Ju KIM, Jung Hoon SONG, Rakhmanov DILSHOD, Dong Hee KIM, Jeon Gjin KIM
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Publication number: 20240107773Abstract: A semiconductor memory device includes a cell string and a first conductive pillar and a second conductive pillar connected to the cell string. The cell string includes plural memory cells, which are stacked on a substrate to be spaced apart from each other. The first conductive pillar is spaced apart from the second conductive pillar in a first direction. Each of the memory cells includes a channel layer that extends from the first conductive pillar to the second conductive pillar in the first direction, a ferroelectric layer on the channel layer, and an electrode on the ferroelectric layer. The channel layer comprises single crystalline silicon.Type: ApplicationFiled: May 17, 2023Publication date: March 28, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: JEON IL LEE, KYUNGHWAN LEE
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Publication number: 20240107774Abstract: A semiconductor memory device includes first through structures on a substrate, the first through structures arranged in a first direction, an electrode adjacent to the first through structures and extending horizontally in the first direction along the first through structures, and a ferroelectric layer interposed between the electrode and the first through structures. Each of the first through structures includes a first conductive pillar and a second conductive pillar spaced apart from each other in the first direction, a channel layer extending from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar, the channel layer interposed between the ferroelectric layer and the first and second conductive pillars, the first and second conductive pillars being spaced apart from each other in the first direction and defining a first air gap. Adjacent ones of the first through structures define a second air gap.Type: ApplicationFiled: May 22, 2023Publication date: March 28, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jeon Il LEE, Kyunghwan LEE
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Publication number: 20240015981Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a bit line that extends in a first direction; first and second word lines that extend in a second direction and cross the bit line; an active pattern on the bit line between the first and second word lines, the active pattern including first second vertical parts that are opposite to each other, and a horizontal part that extends between the first and second vertical parts; a first data storage pattern between the first word line and the first vertical part of the active pattern; a second data storage pattern between the second word line and the second vertical part of the active pattern; and a source line connected to the active pattern, the source line extending the first direction and crossing the first word line and the second word line.Type: ApplicationFiled: April 7, 2023Publication date: January 11, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JEON IL LEE, SERYEUN YANG, HYERAN LEE
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Publication number: 20230422511Abstract: A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.Type: ApplicationFiled: February 21, 2023Publication date: December 28, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Jeon Il LEE, Min Hee CHO
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Patent number: 11840760Abstract: In a layer deposition method, a substrate is loaded into a process chamber. A gas filling tank is charged with a gas to a predetermined charge pressure. The pressure of the gas is elevated to a pressure greater than the predetermined charge pressure. The gas is introduced into the process chamber.Type: GrantFiled: December 3, 2018Date of Patent: December 12, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shin-Jae Kang, Dong-Hoon Han, Do-Hyung Kim, Kyung-Wook Park, Kevin Bae, Sun-Soo Lee, In-Jae Lee, Jeon-Il Lee, Chae-Mook Lim
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Publication number: 20230217646Abstract: A semiconductor device includes a vertical stack of ring-shaped electrodes that are electrically connected together into a top electrode of a capacitor, on a semiconductor substrate. A bottom electrode of the capacitor is also provided, which extends vertically in a direction orthogonal to a surface of the substrate and through centers of the vertical stack of ring-shaped electrodes. An electrically insulating bottom supporting pattern is provided, which extends between a lowermost one of the ring-shaped electrodes and an intermediate one of the ring-shaped electrodes.Type: ApplicationFiled: August 16, 2022Publication date: July 6, 2023Inventors: Jung-Bum Lim, Seungjin Kim, Sangchul Yang, Jeon Il Lee, Hoin Lee
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Publication number: 20230030117Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.Type: ApplicationFiled: April 6, 2022Publication date: February 2, 2023Inventors: Juik LEE, Jong-Min LEE, Jimin CHOI, Yeonjin LEE, Jeon Il LEE
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Patent number: 11508557Abstract: A semiconductor manufacturing apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is configured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.Type: GrantFiled: April 1, 2019Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Joo An, Jeon-Il Lee, Kaoru Yamamoto, Jang-Hee Lee, Kee-Young Jun, Geun-O Jeong
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Patent number: 11120998Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.Type: GrantFiled: September 11, 2018Date of Patent: September 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Lee, Jeon-Il Lee, Sung-Woo Kang, Hong-Sik Shin, Young-Mook Oh, Seung-Min Lee
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Patent number: 10790168Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.Type: GrantFiled: May 7, 2018Date of Patent: September 29, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung Bo Shim, Hyuk Kim, Sun Taek Lim, Jae Myung Choe, Jeon Il Lee, Sung-Il Cho
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Publication number: 20200071822Abstract: A semiconductor manufacturing, apparatus includes a process chamber. An insulating plate divides an interior space of the process chamber into a first space and a second space and thermally isolates the first space from the second space. A gas supplier is co figured to supply a process gas to the first space. A radiator is configured to heat the first space. A stage is disposed within the second space and the stage is configured to support a substrate.Type: ApplicationFiled: April 1, 2019Publication date: March 5, 2020Inventors: Sung-Joo An, Jeon-Il Lee, Kaoru Yamamoto, Jang-Hee Lee, Kee-Young Jun, Geun-O Jeong
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Publication number: 20190164774Abstract: An etching method includes providing a plasma of a first treatment gas to an etching-object to form a deposition layer on the etching-object, the first treatment gas including a fluorocarbon gas and an inert gas, and the etching-object including a first region including silicon oxide and a second region including silicon nitride, providing a plasma of an inert gas to the etching-object having the deposition layer thereon to activate an etching reaction of the silicon oxide, wherein a negative direct current voltage is applied to an opposing part that is spaced apart from the etching-object so as to face an etching surface of the etching-object, the opposing part including silicon, and subsequently, providing a plasma of a second treatment gas to remove an etching reaction product, the second treatment gas including an inert gas and an oxygen-containing gas.Type: ApplicationFiled: September 11, 2018Publication date: May 30, 2019Inventors: Sang-Hyun LEE, Jeon-Il LEE, Sung-Woo KANG, Hong-Sik SHIN, Young-Mook OH, Seung-Min LEE
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Publication number: 20190122903Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.Type: ApplicationFiled: May 7, 2018Publication date: April 25, 2019Inventors: SEUNG BO SHIM, HYUK KIM, SUN TAEK LIM, JAE MYUNG CHOE, JEON IL LEE, SUNG-IL CHO
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Patent number: 10014181Abstract: Methods of forming patterns for semiconductor devices are provided. A method may include preparing a substrate including an etch target layer on a surface of the substrate; forming a mask pattern that includes a lower masking layer having a first density and an upper masking layer having a second density that is less than the first density, on the etch target layer; forming spacers that cover sidewalls of the lower masking layer and the upper masking layer; removing the mask pattern; and etching the etch target layer by using the spacers as an etching mask.Type: GrantFiled: July 20, 2016Date of Patent: July 3, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-soo Lee, Hong-rae Kim, Jeon-il Lee
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Patent number: 9991281Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: GrantFiled: August 8, 2017Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
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Patent number: 9882018Abstract: A semiconductor device includes: a substrate including a channel region; a gate dielectric a tunneling layer, a charge storage layer, and a blocking layer sequentially disposed on the channel region; and a gate electrode disposed on the gate dielectric, wherein the tunneling layer has variations in nitrogen concentrations in a direction perpendicular to the channel region, and has a maximum nitrogen concentration in a position shifted from a center of the tunneling layer toward the charge storage layer.Type: GrantFiled: May 15, 2015Date of Patent: January 30, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Young Jin Noh, Jae Ho Choi, Bio Kim, Kwang Min Park, Jae Young Ahn, Dong Chul Yoo, Seung Hyun Lim, Jeon Il Lee
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Publication number: 20170358596Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: ApplicationFiled: August 8, 2017Publication date: December 14, 2017Inventors: JU-MI YUN, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
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Patent number: 9754959Abstract: A semiconductor device is provided as follows. A tunnel insulation layer is disposed on a substrate. The tunnel insulation layer includes a first silicon oxide layer, a second silicon oxide layer, and a silicon layer interposed between the first silicon oxide layer and the second silicon oxide layer. The silicon layer has a thickness smaller than a thickness of each of the first silicon oxide layer and the second silicon oxide layer. A gate pattern is disposed on the tunnel insulation layer.Type: GrantFiled: December 9, 2015Date of Patent: September 5, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ju-Mi Yun, Young-Jin Noh, Kwang-Min Park, Jae-Young Ahn, Guk-Hyon Yon, Dong-Chul Yoo, Joong-Yun Ra, Young-Seon Son, Jeon-Il Lee, Hun-Hyeong Lim
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Patent number: 9716128Abstract: Active patterns spaced apart from each other by an isolation layer are formed in a substrate. Gate structures extending in the isolation layer through the active patterns are formed. Each active pattern is divided into a central portion and a peripheral portion facing the central portion by the gate structures. A protrusion of at least one of active pattern is formed. The protrusion is exposed from a top surface of the isolation layer, and transformed into silicide such that a first silicide ohmic pad is formed at the central portion of the active pattern and a second silicide ohmic pad is formed at the peripheral portion of the active pattern. A conductive line structure electrically connected to the first silicide ohmic pad is formed. A conductive contact electrically connected to the second silicide ohmic pad is formed. A data storage unit electrically connected to the conductive contact is formed.Type: GrantFiled: March 17, 2015Date of Patent: July 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Kuk Kim, Young-Wook Park, Jeon-Il Lee, Hyun-Jung Lee