Abstract: A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon oxide film. A second chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, an oxide film removal retarder which reduces a removal rate of silicon oxide, and a defect prevention agent which inhibits scratch defects and/or corrosion defects at a surface of an aluminum film. In a one-step CMP process, either of the first or second slurry is used throughout CMP of an aluminum layer until an upper surface of an underlying silicon oxide layer is exposed. In a two-step CMP process, the first slurry is used in an initial CMP of the aluminum layer, and then the second slurry is used in a subsequent CMP until the upper surface of the underlying silicon layer is exposed.

Abstract: Methods of forming ferroelectric layers include forming a ferroelectric layer on a substrate and chemically-mechanically polishing a surface of the ferroelectric layer by rotating a polishing pad on the surface at a rotation speed in a range from about 5 rpm to about 25 rpm. This polishing step includes pressing the polishing pad onto the surface of the ferroelectric layer at a pressure in a range from about 0.5 psi to about 3 psi. This polishing step may be followed by the step of exposing the polished surface to a rapid thermal anneal. This anneal can be performed in an inert atmosphere containing a gas selected from a group consisting of nitrogen, helium, argon and neon.

Abstract: A metallization method for a semiconductor device, and a cleaning solution for the same, for cleaning a surface of a semiconductor substrate on which a metal wiring material is exposed. The metallization method may include cleaning a surface of a semiconductor substrate on which a metal wiring layer is exposed using a cleaning solution that includes deionized water, an organic acid, and at least one of an anionic surfactant and an amphoteric surfactant, and, after the cleaning, ashing the surface of the metal wiring layer.

Abstract: A slurry, chemical mechanical polishing (CMP) method using the slurry, and method of forming metal wiring using the slurry. The slurry may include a polishing agent, an oxidant, and at least one defect inhibitor to protect the metal film. The CMP method and method of forming metal wiring may employ one or two slurries with at least one of the slurries including at least one defect inhibitor.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

Abstract: A first chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, and an oxide film removal retarder which reduces a removal rate of the silicon oxide film. A second chemical mechanical polishing (CMP) slurry includes a polishing agent, an oxidant, a pH control additive, an oxide film removal retarder which reduces a removal rate of silicon oxide, and a defect prevention agent which inhibits scratch defects and/or corrosion defects at a surface of an aluminum film. In a one-step CMP process, either of the first or second slurry is used throughout CMP of an aluminum layer until an upper surface of an underlying silicon oxide layer is exposed. In a two-step CMP process, the first slurry is used in an initial CMP of the aluminum layer, and then the second slurry is used in a subsequent CMP until the upper surface of the underlying silicon layer is exposed.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.