Patents by Inventor Jeong Jun Woo

Jeong Jun Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12166158
    Abstract: A color conversion panel includes light blocking members spaced apart from each other on a substrate; and a first color conversion layer, a second color conversion layer, and a transmission layer respectively disposed between the light blocking members, wherein the transmission layer includes first quantum dots, and the first quantum dots convert incident light into light having a wavelength in a range of about 480 nm to about 530 nm.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: December 10, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeong Ki Kim, Kang Soo Han, Jong-Hoon Kim, Hwa Yeul Oh, Hye Jun Woo
  • Patent number: 12144234
    Abstract: A display device comprises a substrate including display and peripheral areas, a semiconductor element, a pixel structure, and a plurality of dummy patterns. The semiconductor element is disposed in the display area on the substrate, and the pixel structure is disposed on the semiconductor element. The dummy patterns which have stacked structure are disposed in the peripheral area on the substrate, and contain a material identical to a material constituting the semiconductor element. The dummy patterns are arranged in a grid shape in different layers, and each of the dummy patterns includes a central portion and an edge portion surrounding the central portion. The edge portions of dummy patterns which are adjacent to each other in the different layers among the dummy patterns are overlapped each other in a direction from the substrate to the pixel structure.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 12, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sewan Son, Moo Soon Ko, Ji Ryun Park, Jin Sung An, Min Woo Woo, Seong Jun Lee, Wang Woo Lee, Jeong-Soo Lee, Ji Seon Lee, Deuk Myung Ji
  • Patent number: 10734244
    Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 4, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
  • Publication number: 20190148398
    Abstract: Provided is a substrate processing method capable of preventing over-etching of a part of a stair-case structure due to an etching solution, when a barrier layer is selectively formed on a VNAND device having the stair-case structure. The substrate processing method includes: alternately stacking a first insulating layer and a second insulating layer; forming a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface to the lower surface by etching the first insulating layer and the second insulating layer that are stacked; densifying the stepped structure; forming a barrier layer on the densified second insulating layer; and performing isotropic etching on at least a part of a sacrificial word line structure including the second insulating layer and the barrier layer. During etching the barrier layer at the isotropic etching step, the second insulating layer is not etched or etched a little to an ignorable degree.
    Type: Application
    Filed: July 19, 2018
    Publication date: May 16, 2019
    Inventors: Young Hoon Kim, Jong Wan Choi, Jeong Jun Woo, Tae Hee Yoo
  • Patent number: D724553
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 17, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Woo Choi, Hyung Wook Noh, Jeong Jun Woo, Dae Youn Kim, Hyun Soo Jang
  • Patent number: D880437
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: April 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Hak Joo Lee, Jeong Jun Woo, Jong Hyun Ahn, Yoon Ki Min
  • Patent number: D913980
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: March 23, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Hak Joo Lee, Jeong Jun Woo, Jong Hyun Ahn, Yoon Ki Min