Redundancy program circuit and methods thereof
A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.
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This U.S. nonprovisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Applications 2004-50226 filed on Jun. 30, 2004 and 2004-72371 filed on Sep. 10, 2004, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates generally to a semiconductor device and methods thereof, and more particularly, to a redundancy program circuit and methods thereof.
2. Description of Related Art
A fabrication of a semiconductor device (e.g., a semiconductor memory device) may include various tests (e.g., of chips or memory devices on a wafer) to verify a correct function of the semiconductor device. For example, such tests may verify whether circuit devices in the semiconductor device may operate in conformity with a given specification or protocol. In an example test, a plurality of test parameters may be used to check electrical characteristics and/or an operation of a tested semiconductor device. If the given test indicates an incorrect operation of the tested semiconductor device (e.g., because the electrical characteristics and/or the operation of the semiconductor may not be proper), a debugging of the semiconductor device may not be possible.
However, in an example where the semiconductor device may include a defective memory cell within a memory cell array, a repair process (e.g., debugging process) may be executed which may replace the defective memory cell with a redundancy memory cell. In other words, if a portion of the memory cells in the semiconductor device are defective, the defective portion of the memory cells may be replaced with at least one spare memory cell manufactured redundantly, which may thereby enable the semiconductor device to operate correctly.
A redundancy program circuit, which may be alternatively referred to as a fuse box or spare circuit, may be employed to achieve the above described debugging or defective memory cell replacement process. The redundancy program circuit may employ a process which may include melting fuses (e.g., with a high energy light, a laser, etc.), as will be described below in greater detail with reference to
In
The row/column internal address generators 4/5 may be integrated such that an internal address (e.g., a row or column address) may be generated. The row/column predecoder 6/7 may predecode the internal address and may generate, for example, a predecoded address having 16 bits (e.g., DA01 4 bit+DA234 8 bit+DA56 4 bit). The row decoder 20 may decode the predecoded row address DRAi and may select a given word line from among the word lines WL0:n of the normal memory cell array 41 and the row spare circuit 10 may generate a row redundancy enable signal X-RENi for replacing a given row of a defective memory cell in response to the predecoded row address DRAi.
Similarly, the column decoder 30 may decode the predecoded column address DCAi, and may select a given column selection line from among a plurality of column selection lines of the normal memory cell array 41. The column spare circuit 11 may generate a column redundancy enable signal Y-RENi for replacing a given column of a defected memory cell in response to the predecoded column address DCAi.
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If the normal memory cell array 41 includes a defective memory cell and a row and/or column address for designating the defective memory cell is applied (e.g., during operation), the row spare circuit 10 and/or column spare circuit 11 may output a redundancy enable signal RENi to disable a row and/or column of the defective memory cell and may enable a row or column of a redundant memory cell (e.g., based on a cutting of the fuses F1-F16). In an example, referring to
If a normal disable signal at a second logic level (e.g., a lower logic level, a higher logic level, etc.) is applied to the row/column decoder 20/30, the row/column decoder 20/30 may disable a corresponding normal row or normal column. A row or column of a defective memory cell may be set at an inoperable state (e.g., not capable of a reading or writing to/from the memory). The redundancy enable signal RENi may also be applied to a spare row/column decoder 25/35. A row or column of the spare memory cell may be enabled and the defective memory cell may be replaced with a redundant spare memory cell.
In other words, a defective memory cell may be replaced by cutting or blowing a master fuse among fuses MF and F1-F16 in the row/column spare circuits 10/11 and a fuse corresponding to an address bit of the defective memory cell.
In the above-described conventional redundancy program operation, a manufacturing yield of semiconductor devices may be increased by repairing a defective memory cell. However, a chip size and a duration of the redundancy program operation may scale with a number of fuses. For example, if the conventional semiconductor device 107 requires additional memory, it may also require additional fuses for the redundancy program operation (e.g., because more bits may be needed to address the additional memory), thereby requiring a larger chip size which may reduce a yield of the semiconductor device 107 and induce a longer duration for each defective memory cell replacement (e.g., because multiple fuses may be cut/blown), thereby reducing a speed of operation.
Further, the fuses F1-F16 of
An example embodiment of the present invention is directed to a redundancy program circuit, including a master fuse circuit including a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.
Another example embodiment of the present invention is direct to a redundancy program circuit, including a master fuse circuit including a master fuse generating an operation enable signal indicating an operating status of the master fuse, a first fuse box circuit including first program fuses disposed so as to correspond to signal bits of a decoding address and generating a first fuse box output signal in response to the operation enable signal, a second fuse box circuit including second program fuses disposed so as to correspond to signal bits of an internal address and generating a second fuse box output signal in response to the operation enable signal and a gating circuit for gating the first and second fuse box output signals and generating a redundancy enable signal.
Another example embodiment of the present invention is directed to a method of performing a redundancy program operation, including generating an operation enable signal, generating at least one control signal pair, selectively outputting logic levels of at least a portion of a decoding address based at least in part on a first of the at least one control signal pair and multiplexing the selectively outputted logic levels to attain a redundancy enable signal based at least in part on the at least one control signal pair.
Another example embodiment of the present invention is directed to a method of performing a redundancy program operation, including generating an operation enable signal, generating a first fuse box output signal based on whether the operation enable signal is activated, generating a second fuse box output signal at a program fuse disposed so as to correspond to signal bits of an internal address generated before an applied external address is decoded and gating the first and second fuse box output signals to generate a redundancy enable signal.
Another example embodiment of the present invention is directed to a method of reducing the number of fuses used for a redundancy program operation, including allocating a first portion of fuses corresponding to signal bits of a decoding address and allocating a second portion of fuses corresponding to signal bits of an internal address.
Another example embodiment of the present invention is directed to a redundancy program circuit, including a master fuse circuit including a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a decoding circuit for decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level along with the decoding address to a decoding output terminal.
Another example embodiment of the present invention is directed to a method of performing a redundancy program operation, including generating an operation enable signal, generating an operating status signal indicating a status of at least one control fuse and decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level associated with a defective memory cell along with the decoding address to a decoding output terminal.
BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings are included to provide a further understanding of example embodiments of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate example embodiments of the present invention and, together with the description, serve to explain principles of the present invention. In the drawings:
Hereinafter, example embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the Figures, the same reference numerals are used to denote the same elements throughout the drawings. However, a number of transistors (e.g., NMOS transistors, PMOS transistors, etc.) are included in the Figures. It is understood that, while certain transistors in different figures include like numbering, the similarly named transistors may be the same or different in example embodiments of the present invention.
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Hereafter, for purposes of explanation, a given terminal receiving a signal bit (e.g., DA01<0>) of a decoding address to perform a redundancy operation, may be referred to as a first output terminal. In an example, the first output terminal may correspond to the output terminal OU1 and other output terminals may be separated from the program output terminal FO1.
In another example embodiment of the present invention, during a redundancy operation, referring to the second multiplexer 430, only a given logic level of the first output terminal (e.g., output terminal OU1) may be transferred to the program output terminal FO1. Other output terminals (e.g., output terminal OU2) may be separated from the program output terminal FO1.
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An output EN of the inverter latch L1 may transition to the first logic level and the operation enable signal ENB (e.g., the output of the output inverter IN3) may transition to the second logic level. When the power-up bar signal VCCHB transitions to the second logic level, the NMOS transistor NM1 may be turned off and the output EN of the inverter latch L1 may be maintained at the first logic level. The power-up bar signal VCCHB and the operation enable signal ENB may be maintained at the second logic level for a given period of time.
In another example, if the outputs control signal A and /A of the control signal pair A,/A are set to the first logic level and the second logic level, respectively, the NMOS transistor NM1 may be turned on when the power-up bar signal VCCHB is applied at the first logic level such that the control fuse F1 may be cut. The control signal A (e.g., of the control signal pair A,/A) of the inverter latch L2 may transition to the first logic level, and the control signal /A of NOR gate NOR1 (e.g., for NOR-gating the operation enable signal ENB and the control signal A) may transition to the second logic level. When the power-up bar signal VCCHB transitions to the second logic level, the NMOS transistor NM1 may be turned off and the control signal A of the inverter latch L2 may be maintained at the first logic level. Thus, the power-up bar signal VCCHB and the control signals A and /A of the control signal pair A,/A may be maintained at their respective logic levels for a given period of time.
Further, in another example, if the control signals B and /B of the control signal pair B,/B are generated at the first logic level and the second logic level, respectively, the operation of the second control fuse 330 may be similar as the above-described example with respect to first control fuse 310 where the control signals A and /A of the control signal pair A,/A are set to the first and second logic levels, respectively.
In another example, if the operation enable signal ENB is activated, the control signal pair A,/A and the control signal pair B,/B may transition to the second logic level, the first logic level, the second logic level, the first logic level and the second logic level, respectively, the operation enable transistor 450 may be turned off, transistors M1 and M4 of the first multiplexer 410 may be turned on, and a transistor M5 of second multiplexer 430 may be turned on. The redundancy enable signal RENi may transition to the first logic level and may be outputted to the program output terminal F01. The redundancy enable signal RENi may correspond to the signal bit DA01<0>of the decoding address, for example, the address (00). A redundancy operation may be performed for the address (00) by cutting the master fuse MF and the control fuses F1 and F2, (e.g., when the redundancy enable signal RENi may be activated when an address of (00) may be applied in a normal operation of a semiconductor device (e.g., a semiconductor memory device)) thereby debugging or correcting operation for a semiconductor device including the redundancy program circuit 405.
Alternatively, in another example, if a redundancy operation is performed for address (01), a signal bit DA01<1>of the decoding address may correspond to address (01) and the master fuse MF and the control fuse F2 may be cut. In another alternative example, if a redundancy operation is performed for address (10), a signal bit DA01<1>of the decoding address may correspond to address (10) and the master fuse MF may be cut. In another alternative example, if a redundancy operation is performed for address (11), a signal bit DA01<1>of the decoding address may correspond to address (11) and the master fuse MF and the control fuse F1 may be cut.
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In an alternative example embodiment of the present invention, if signal bits of a decoding address are increased to 16 bits, a redundancy control circuit (e.g., redundancy program circuit 405) may include a higher number of control fuses (e.g., seven) and a number of multiplexers.
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In another example embodiment of the present invention, control fuses may be installed within control fuse circuit 300 and the redundancy enable signal RENi may be generated with a multiplexing operation. The above-described example embodiment may allow a reduction (e.g., a half-reduction) for signal bits of the decoding address and the number of fuses used for a redundancy program may thereby be reduced. The reduced number of fuses may reduce a chip size. Further, a number of cutting operations may be reduced by the reduction of the number of fuses, thereby increasing an efficiency and speed of a redundancy operation (e.g., a repair or debugging time for semiconductor devices including the redundancy program circuit 405).
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In another example embodiment of the present invention, the program fuse circuit 440 may transfer a logic level received from the first output terminal OU1 to the program output terminal FO1 through fuse FU1 connected to the first output terminal OU1. The output terminal OU2 may not operatively connected to the program output terminal FO1 because of a cutting of fuse FU2 which may be connected to at least one output terminal OU2 that may be independent or separate from the first output terminal OU1. In an alternative example, the fuse FU2 may be non-cut and the fuse FU1 may be cut (e.g., based on another received signal bit for the redundancy operation).
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In another example, signal bits (DA01<0>, DA01<1>, DA01<2>, DA01<3>) may correspond to (00, 01, 10, 11), respectively. In a further example, the redundancy enable signal RENi may correspond to the signal bit DA01<0> of the decoding address, for example, the address (00). A redundancy operation may be performed at address (00) by cutting the master fuse MF, the control fuse F1, and the program fuse FU2 when the redundancy enable signal RENi is activated for the address (00) (e.g., when the address (00) may be applied in a normal operation of a semiconductor device (e.g., a semiconductor memory device)), thereby debugging or correcting operation for the semiconductor device.
Alternatively, in another example, the redundancy enable signal RENi may correspond to the signal bit DA01<1> of the decoding address, for example, the address (01). A signal bit DA01<1> of the decoding address may correspond to address (01) and the master fuse MF and the program fuse FU2 may be cut. In another alternative example, the redundancy enable signal RENi may correspond to the signal bit DA01<2> of the decoding address, for example, the address (10). A signal bit DA01<2> of the decoding address may correspond to address (10) and the master fuse MF and the program fuse FU1 may be cut. In another alternative example, the redundancy enable signal RENi may correspond to the signal bit DA01<3> of the decoding address, for example, the address (11). A signal bit DA01<3> of the decoding address may correspond to address (11) and the master fuse MF, the control fuse F1, and the program fuse FU1 may be cut.
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The operation enable transistor 450 may be turned off, transistors M1 and M4 of multiplexer 420 may be turned on, and the program fuse FU1 may not be cut. Thus, the redundancy enable signal RENi may be output at the first logic level to the program output terminal F01. The received redundancy enable signal RENi may correspond to a signal bit DA01<0> of the decoding address, which may the address (00). A redundancy operation may be required to debug a semiconductor device by cutting the master fuse MF, the control fuses F1 and the program fuse FU1 (e.g., when an address (00) of a defective memory cell may be applied during operation of a semiconductor device).
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An example of a redundancy program operation for the second fuse box circuit 100 of FIGS. 13 will now be described.
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Alternatively, if the fuse F9 is cut, the input logic of signal bit IADD<2> may be cut off (e.g., the logic level may be the second logic level irrespective of the logic level of the signal bit IADD<2>). A signal path through transistor N11, transistor N13 and program output terminal FO2 may be activated and the signal bit IADD<2> of an internal address inverted by inverter IN1 may be applied as an input of the NAND gate NAN2.
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In another example embodiment of the present invention, instead of a one-to-one ratio between fuses and signal bit of a decoding row address or decoding column address, a redundancy operation may be performed using combinational logic. The redundancy enable signal may thereby be generated at a higher speed. Further, a given number of fuses required may be reduced. Further, a duration allocated to a redundancy operation may be reduced (e.g., because a cutting time for given fuses in the redundancy operation may be reduced).
In another example embodiment of the present invention, a number of fuses used for a redundancy operation may be reduced, which may thereby reduce a chip area for a semiconductor device, which may thereby reduce a repair time for the semiconductor device.
Example embodiments of the present invention being thus described, it will be obvious that the same may be varied in many ways. For example, while logic levels are above-described as transitioning to either the first or second logic level, it is understood that the first or second logic levels may be transitioned to or from either the first or second logic level. In other words, “transition” may not necessarily mean that a previous logic level differed from the logic level transitioned to.
Further, it is understood that the above-described first and second logic levels/states may correspond to a higher level (e.g., a logic “1”) and a lower logic level (e.g., a logic “0”), respectively, in an example embodiment of the present invention. Alternatively, the first and second logic levels/states may correspond to the lower logic level and the higher logic level, respectively, in other example embodiments of the present invention.
Further, while above-described example circuits (e.g., row/column spare circuits 10a/11a, etc.) include a given number of fuses, it is understood that other example embodiments of the present invention may include any number of fuses (e.g., based on an internal/external, decoded/undecoded address length).
Further, while the AND gate/combination circuit 500 is above-described and illustrated as an AND gate, it is understood that other example embodiments of the present invention may employ other types of combinational logic (e.g., a NOR gate, a NAND gate, etc.).
Such variations are not to be regarded as departure from the spirit and scope of example embodiments of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Claims
1-19. (canceled)
20. A redundancy program circuit, comprising:
- a master fuse circuit including a master fuse generating an operation enable signal indicating an operating status of the master fuse;
- a first fuse box circuit including first program fuses disposed so as to correspond to signal bits of a decoding address and generating a first fuse box output signal in response to the operation enable signal;
- a second fuse box circuit including second program fuses disposed so as to correspond to signal bits of an internal address and generating a second fuse box output signal in response to the operation enable signal; and
- a gating circuit for gating the first and second fuse box output signals and generating a redundancy enable signal.
21. The redundancy program circuit of claim 20, wherein the operating status indicates whether or not the master fuse is cut.
22. The redundancy program circuit of claim 20, wherein the redundancy enable signal is received by a redundancy row decoder or a redundancy column decoder.
23. The redundancy program circuit of claim 20, wherein the decoding address is an address output from a predecoder and the internal address is an address received by the predecoder.
24. A method of performing a redundancy program operation, comprising:
- generating an operation enable signal;
- generating at least one control signal pair;
- selectively outputting logic levels of at least a portion of a decoding address based at least in part on a first of the at least one control signal pair; and
- multiplexing the selectively outputted logic levels to attain a redundancy enable signal based at least in part on the at least one control signal pair.
25. The method of claim 24, wherein the redundancy enable signal is based on at least one control signal pair other than the first of the at least one control signal pair.
26. The method of claim 24, wherein the multiplexing includes reducing signal bits of the decoding, the reduced portion decoding address being the redundancy enable signal.
27. The method of claim 24, wherein the at least one control signal pair indicates an operating status of a corresponding control fuse.
28. A method of performing a redundancy program operation, comprising:
- generating an operation enable signal;
- generating a first fuse box output signal based on whether the operation enable signal is activated;
- generating a second fuse box output signal at a program fuse disposed so as to correspond to signal bits of an internal address generated before an applied external address is decoded; and
- gating the first and second fuse box output signals to generate a redundancy enable signal.
29. A method of reducing the number of fuses used for a redundancy program operation, comprising:
- allocating a first portion of fuses corresponding to signal bits of a decoding address; and
- allocating a second portion of fuses corresponding to signal bits of an internal address.
30. The method of claim 29, wherein the internal address is generated before predecoding an external address.
31. A redundancy program circuit, comprising:
- a master fuse circuit including a master fuse outputting an operation enable signal to indicate a master fuse operating status;
- at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse in response to the operation enable signal; and
- a decoding circuit for decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level along with the decoding address to a decoding output terminal.
32. The redundancy program circuit of claim 31, wherein the decoding address is decoded from one of an internal address generated before predecoding and an external address received from an external device.
33. The redundancy program circuit of claim 31, wherein the decoding circuit includes a plurality of decoders, a number of the plurality of decoders corresponding to a number of signal bits in the decoding address.
34. The redundancy program circuit of claim 33, wherein each of the plurality of decoders includes at least one NMOS transistor.
35. The redundancy program circuit of claim 34, wherein the at least one NMOS transistor for each of the plurality of decoders includes channels connected in series.
36. The redundancy program circuit of claim 31, wherein:
- the at least one control fuse circuit includes a plurality of control fuse circuits which are controlled in response to the operation enable signal of the master fuse circuit, the at plurality of control fuse circuits including a number of control fuses corresponding to a number of decoding address signal bits of the decoding address; and
- the decoding circuit is one of a plurality of decoding circuits, each of the plurality of decoding circuits outputting the given logic level to a corresponding output terminal.
37. The redundancy program circuit of claim 36, further comprising:
- a combination circuit for gating the logic levels received from the plurality of decoding circuits at the corresponding output terminals and generating a redundancy enable signal as a result of the gating operation.
38. The redundancy program circuit of claim 36, wherein the number of control fuses within the plurality of control fuse circuits equals the number of decoding address signal bits of the decoding address.
39. The redundancy program circuit of claim 37, wherein the operating status signal includes three control signal pairs when the decoding address includes eight signal bits.
40. The redundancy program circuit of claim 39, wherein the eight signal bits of the decoding address are decoded by eight combinational logic inputs generated based on the three control signal pairs.
41. The redundancy program circuit of claim 37, wherein the combination circuit includes an AND gate.
42. A method of performing a redundancy program operation, comprising:
- generating an operation enable signal;
- generating an operating status signal indicating a status of at least one control fuse; and
- decoding signal bits of a decoding address in response to the operating status signal and transferring a given logic level associated with a defective memory cell along with the decoding address to a decoding output terminal.
Type: Application
Filed: Oct 30, 2007
Publication Date: Mar 6, 2008
Patent Grant number: 7477565
Applicant:
Inventors: Jeong-Sik Nam (Seoul), Sang-Kyun Park (Suwon-si), Kwang-Hyun Kim (Seoul), Byung-Sik Moon (Seoul), Won-Chang Jung (Suwon-si)
Application Number: 11/978,579
International Classification: G11C 29/00 (20060101); G11C 17/18 (20060101);