Patents by Inventor Jeong Soo Byun
Jeong Soo Byun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200287056Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.Type: ApplicationFiled: March 16, 2020Publication date: September 10, 2020Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Soo Byun
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Publication number: 20200161478Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.Type: ApplicationFiled: May 24, 2019Publication date: May 21, 2020Inventors: Krishnaswarmy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Publication number: 20200161324Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: ApplicationFiled: June 7, 2019Publication date: May 21, 2020Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 10593812Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.Type: GrantFiled: June 5, 2018Date of Patent: March 17, 2020Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Patent number: 10319733Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: GrantFiled: September 19, 2018Date of Patent: June 11, 2019Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 10304968Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: GrantFiled: January 26, 2015Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Patent number: 10269985Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: GrantFiled: January 26, 2015Date of Patent: April 23, 2019Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Publication number: 20190088669Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: ApplicationFiled: September 19, 2018Publication date: March 21, 2019Applicant: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Publication number: 20180351004Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.Type: ApplicationFiled: June 5, 2018Publication date: December 6, 2018Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Patent number: 10128258Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasm oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: GrantFiled: September 15, 2016Date of Patent: November 13, 2018Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 10090416Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: GrantFiled: January 26, 2015Date of Patent: October 2, 2018Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Publication number: 20170005108Abstract: A method of making and structural embodiments of a semiconductor structure are provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate, forming a charge storage layer overlying the tunneling layer, and forming a blocking structure on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described.Type: ApplicationFiled: September 15, 2016Publication date: January 5, 2017Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 9460974Abstract: A method of making a semiconductor structure is provided. The method includes forming a tunneling layer overlying a first channel connecting a source and a drain. A charge storage layer is formed overlying the tunneling layer, the charge storage layer comprises forming a substantially trap free first layer over the tunneling layer, and forming a trap dense second layer over the first layer. Finally, a blocking structure is formed on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described.Type: GrantFiled: December 15, 2015Date of Patent: October 4, 2016Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 9406574Abstract: A method of making a semiconductor structure is provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate, forming a charge storage layer overlying the tunneling layer, and forming a blocking structure on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described.Type: GrantFiled: December 5, 2014Date of Patent: August 2, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Publication number: 20150187960Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: ApplicationFiled: January 26, 2015Publication date: July 2, 2015Inventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Patent number: 9031685Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.Type: GrantFiled: January 7, 2014Date of Patent: May 12, 2015Assignee: Applied Materials, Inc.Inventors: Barry L. Chin, Alfred W. Mak, Lawrence C. Lei, Ming Xi, Hua Chung, Ken Kaung Lai, Jeong Soo Byun
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Patent number: 8822349Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.Type: GrantFiled: February 21, 2012Date of Patent: September 2, 2014Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Publication number: 20140130739Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.Type: ApplicationFiled: January 7, 2014Publication date: May 15, 2014Inventors: Barry L. CHIN, Alfred W. MAK, Lawrence C. LEI, Ming XI, Hua CHUNG, Ken Kaung LAI, Jeong Soo BYUN
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Patent number: 8691648Abstract: Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.Type: GrantFiled: June 24, 2011Date of Patent: April 8, 2014Assignee: Cypress Semiconductor CorporationInventors: Igor Polishchuk, Sagy Levy, Krishnaswamy Ramkumar, Jeong Soo Byun
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Patent number: 8626330Abstract: A method and apparatus for atomic layer deposition (ALD) is described. In one embodiment, an apparatus comprises a vacuum chamber body having a contiguous internal volume comprised of a first deposition region spaced-apart from a second deposition region, the chamber body having a feature operable to minimize intermixing of gases between the first and the second deposition regions, a first gas port formed in the chamber body and positioned to pulse gas preferentially to the first deposition region to enable a first deposition process to be performed in the first deposition region, and a second gas port formed in the chamber body and positioned to pulse gas preferentially to the second deposition region to enable a second deposition process to be performed in the second deposition region is provided.Type: GrantFiled: September 19, 2011Date of Patent: January 7, 2014Assignee: Applied Materials, Inc.Inventors: Barry L. Chin, Alfred W. Mak, Lawrence Chung-Lai Lei, Ming Xi, Hua Chung, Ken Kaung Lai, Jeong Soo Byun