Patents by Inventor Jeremy D. Ecton
Jeremy D. Ecton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12353070Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.Type: GrantFiled: September 9, 2021Date of Patent: July 8, 2025Assignee: Intel CorporationInventors: Hiroki Tanaka, Brandon C Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D Ecton, Hari Mahalingam, Benjamin Duong
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Patent number: 12354883Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.Type: GrantFiled: September 24, 2021Date of Patent: July 8, 2025Assignee: Intel CorporationInventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
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Publication number: 20250218952Abstract: Embodiments disclosed herein include components that are embedded within a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a cavity is provided through a thickness of the substrate, and a first layer is in the cavity. In an embodiment, the first layer has a first width. In an embodiment, a component is on the first layer, and the component has a second width that is smaller than the first width. In an embodiment, a second layer is provided between a sidewall of the cavity and a sidewall of the component.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Benjamin DUONG, Tolga ACIKALIN, Soham AGARWAL, Jeremy D. ECTON, Kari HERNANDEZ, Brandon C. MARIN, Pratyush MISHRA, Pratyasha MOHAPATRA, Srinivas Venkata Ramanuja PIETAMBARAM, Marcel SAID, Bohan SHAN, Gang DUAN
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Publication number: 20250218965Abstract: Assemblies that include package substrates and semiconductor chips are provided. The package substrates include interconnect bridges having through-bridge vias. The assemblies also include alignment features and receiving cavities.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Brandon C. MARIN, Jeremy D. ECTON, Srinivas PIETAMBARAM, Gang DUAN
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Publication number: 20250218915Abstract: An apparatus comprising a package substrate comprising a core layer; a pedestal embedded in the core layer; and a structure comprising a passive circuit component, wherein the structure is above the pedestal and is embedded in the core layer.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Tolga Acikalin, Soham Agarwal, Benjamin T. Duong, Jeremy D. Ecton, Kari E. Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas V. Pietambaram, Marcel M. Said, Gang Duan, Hiroki Tanaka, Robert A. May, Bai Nie, Sanjay Tharmarajah, Bohan Shan
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Publication number: 20250218904Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Ziyin Lin, Bohan Shan, Kyle J. Arrington, Ryan Joseph Carrazzone, Jose Fernando Waimin Almendares, Hongxia Feng, Srinivas Venkata Ramanuja Pietambaram, Hiroki Tanaka, Haobo Chen, Gang Duan, Brandon Christian Marin, Yongki Min, Dingying Xu, Clay Bradley Arrington, Jeremy D. Ecton, Suddhasattwa Nad
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Publication number: 20250218898Abstract: Embodiments disclosed herein include components that include passive electrical devices with a thickness augmentation. In an embodiment, such an apparatus comprises a substrate with a first material composition, and a liner on a sidewall of the substrate. In an embodiment, a layer is on the substrate, where the layer has a second material composition that is different than the first material composition. In an embodiment, the layer directly contacts at least a portion of a surface of the substrate.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Jeremy D. ECTON, Brandon C. MARIN, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Benjamin DUONG
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Publication number: 20250218998Abstract: Embodiments disclosed herein include an apparatus that comprises a first substrate and a second substrate over the first substrate. In an embodiment, an array of interconnects is provided between the first substrate and the second substrate. The array of interconnects comprises a first interconnect with a first material composition, and a second interconnect with a second material composition that is different than the first material composition.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Bohan SHAN, Shripad GOKHALE, Rui ZHANG, Mine KAYA, Haobo CHEN, Steve S. CHO, Timothy GOSSELIN, Kartik SRINIVASAN, Edvin CETEGEN, Kyle ARRINGTON, Nicholas S. HAEHN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Ashay DANI, Yoshihiro TOMITA, Ziyin LIN, Yiqun BAI, Jose WAIMIN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Jung Kyu HAN, Liang HE
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Publication number: 20250219040Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Inventors: Tolga ACIKALIN, Soham AGARWAL, Benjamin T. DUONG, Jeremy D. ECTON, Kari E. HERNANDEZ, Brandon Christian MARIN, Pratyush MISHRA, Pratyasha MOHAPATRA, Srinivas Venkata Ramanuja PIETAMBARAM, Marcel M. SAID, Suddhasattwa NAD, Gang DUAN, Zhixin XIE, Jung Kyu HAN, Mohamed R. SABER, Shuren QU, Naiya SOETAN-DODD, Teng SUN, Yuxin FANG
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Publication number: 20250218962Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Mahdi Mohammadighaleni, Yosef Kornbluth, Shayan Kaviani, Ehsan Zamani, Kihyun Kim, Srinivas Venkata Ramanuja Pietambaram, Dilan Seneviratne, Elham Tavakoli, Whitney M. Bryks, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Suddhasattwa Nad
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Publication number: 20250218982Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors and multi-layer ceramic capacitors (MLCCs) are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.Type: ApplicationFiled: December 28, 2023Publication date: July 3, 2025Applicant: Intel CorporationInventors: Suddhasattwa Nad, Jeremy D. Ecton, Brandon Christian Marin, Gang Duan, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20250210469Abstract: Embodiments disclosed herein comprise an apparatus. In an embodiment, the apparatus comprises a substrate with a first cavity into the substrate. In an embodiment, the first cavity has a first depth. In an embodiment, a second cavity is provided into the substrate, where the second cavity has a second depth that is different than the first depth. In an embodiment, a first die is in the first cavity, where the first die has a first thickness. In an embodiment, a second die is in the second cavity, where the second die has a second thickness that is different than the first thickness.Type: ApplicationFiled: December 20, 2023Publication date: June 26, 2025Inventors: Brandon C. MARIN, Numair AHMED, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Benjamin DUONG, Suddhasattwa NAD, Bohan SHAN
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Publication number: 20250201787Abstract: Apparatus and methods for embedding deep trench capacitors (DTCs) in a package substrate. The method includes fabricating an integrated circuit on a silicon substrate core and identifying a deep trench capacitor (DTC) component to integrate with the integrated circuit. A cavity is created in the silicon substrate core to accommodate the DTC component. The cavity extends therethrough, like a through-hole. A temporary carrier is attached to the silicon substrate to create a cavity floor. A gap magnitude is determined, which is a difference between the thickness of the silicon substrate core and the thickness of the DTC component. An epoxy material with a minimum bond line that matches the gap magnitude is selected and implemented to fill the gap in fabrication. The minimum bond line is controlled by selection of particles to use in the epoxy material.Type: ApplicationFiled: December 18, 2023Publication date: June 19, 2025Applicant: Intel CorporationInventors: Marcel M. Said, Tolga Acikalin, Soham Agarwal, Benjamin T. Duong, Jeremy D. Ecton, Kari E. Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas Venkata Ramanuja Pietambaram
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Publication number: 20250192059Abstract: Embodiments disclosed herein include bridge structures for package substrates. In an embodiment, a package substrate comprises a substrate that is a dielectric material. In an embodiment, a cavity is formed into the substrate. A first pad is on a bottom surface of the cavity, and a die is at least partially in the cavity. In an embodiment, a via passes through at least a portion of a thickness of the die, and a second pad is on the die. In an embodiment, the second pad directly contacts the first pad, and the first pad is the only electrically conductive structure between the via and the second pad.Type: ApplicationFiled: December 6, 2023Publication date: June 12, 2025Inventors: Brandon C. MARIN, Minglu LIU, Bohan SHAN, Bainye Francoise ANGOUA, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Numair AHMED, Jeremy D. ECTON, Benjamin DUONG, Hongxia FENG, Bai NIE, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Andrey GUNAWAN, Yingying ZHANG, Yosuke KANAOKA, Yosef KORNBLUTH, Aaditya Anand CANDADAI, Daniel ROSALES-YEOMANS, Jieying KONG, Shuqi LAI, Ao WANG, Joshua STACEY, Dilan SENEVIRATNE, Jade Sharee LEWIS
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Publication number: 20250183180Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.Type: ApplicationFiled: December 5, 2023Publication date: June 5, 2025Inventors: Brandon C. MARIN, Robert Alan MAY, Minglu LIU, Bohan SHAN, Jason M. GAMBA, Lilia MAY, Tarek A. IBRAHIM, Hiroki TANAKA, Srinivas Venkata Ramanuja PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD, Benjamin DUONG, Haobo CHEN, Xiao LIU, Xiyu HU, Wei WEI, Bai NIE, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Dingying David XU, Bin MU, Mohit GUPTA, Xiaoying GUO, Yiqun BAI
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Publication number: 20250183179Abstract: Embodiments disclosed herein comprise bridge dies with embedded passive components. In an embodiment, the bridge die is an apparatus that comprises a substrate with a via at least partially through a thickness of the substrate. In an embodiment, the via is electrically conductive. In an embodiment, a shell is provided around a perimeter of the via, and the shell is a different material than the via.Type: ApplicationFiled: December 4, 2023Publication date: June 5, 2025Inventors: Brandon C. MARIN, Mohamed R. SABER, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Jeremy D. ECTON, Suddhasattwa NAD, Benjamin DUONG, Bohan SHAN, Sashi S. KANDANUR, Cary KULIASHA, Shruti SHARMA, Mollie STEWART, Rahul N. MANEPALLI, Kristof DARMAWIKARTA
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Publication number: 20250112164Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250106983Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
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Publication number: 20250087587Abstract: Architectures and process flows for an embedded organic bridge component for semiconductor packages. The bulk of the substrate package fabrication can be done using conventional processing steps to meet core geometries (e.g., 9/12) with associated equipment and clean room protocols. Separately the organic bridge component is fabricated to embed into the substrate package at a location where the high-speed input/output (I/O) performance and high-density (HD) geometry are required. The organic bridge component is fabricated as required to meet the HD geometry (e.g., 3/3, or less). During assembly, the embedded organic bridge component can be attached into a cavity in the substrate package.Type: ApplicationFiled: September 12, 2023Publication date: March 13, 2025Applicant: Intel CorporationInventor: Jeremy D. Ecton
