Patents by Inventor Jeremy D. Ecton

Jeremy D. Ecton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250004380
    Abstract: Devices, systems, and methods for conditioning a solvent return flow from a photolithographic process used for semiconductor processing are presented. Reuse of materials in semiconductor processing can provide environmental and manufacturing cost advantages. Devices for conditioning a solvent return flow from a photolithographic process and systems for photolithographic processes include a baffle system and a light system. Methods for reusing a solvent from a photolithographic process include passing the solvent through a conditioning device having a baffle system and a light system.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Inventors: Joseph BLOXHAM, Jeremy D. ECTON
  • Publication number: 20240339381
    Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.
    Type: Application
    Filed: April 4, 2023
    Publication date: October 10, 2024
    Inventors: Hiroki TANAKA, Veronica STRONG, Henning BRAUNISCH, Haobo CHEN, Jeremy D. ECTON, Kristof DARMAWIKARTA, Brandon C. MARIN
  • Publication number: 20240222248
    Abstract: Architectures and methods for metal lamination on a glass layer or glass core. The architectures implement dummy anchors to prevent or reduce the delamination of conductive materials from glass surfaces. The anchors hold the conductive pads and conductive material planes down to the glass surface. The architecture includes various combinations of end anchors and through glass via (TGV) anchors.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Sashi Shekhar Kandanur, Srinivas V. Pietambaram, Gang Duan, Jeremy D. Ecton
  • Publication number: 20240222130
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core. In an embodiment, the TGV comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Shaojiang CHEN, Jeremy D. ECTON, Oladeji FADAYOMI, Hsin-Wei WANG, Changhua LIU, Bin MU, Hongxia FENG, Brandon C. MARIN, Srinivas V. PIETAMBARAM
  • Publication number: 20240222279
    Abstract: Technologies for a vertically interconnected glass layer architecture is disclosed. In the illustrative embodiment, an integrated circuit component includes several integrated circuit dies and a glass layer. Integrated circuit dies are positioned both above and below the glass layer. The glass layer has a bridge die embedded in a cavity. The bridge die provides interconnects between the various dies and to other components off of the integrated circuit component. The glass layer can enable three-dimensional heterogeneous integration, allowing for fine pitch connections between dies.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Gang Duan, Suddhasattwa Nad
  • Publication number: 20240222137
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core, where a top surface of the TGV is not coplanar with a top surface of the core. In an embodiment, the electronic package further comprises a ridge on the top surface of the TGV, where the ridge is symmetric about a centerline of the TGV.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Shaojiang CHEN, Jeremy D. ECTON, Oladeji FADAYOMI, Srinivas V. PIETAMBARAM, Matthew L. TINGEY
  • Publication number: 20240219655
    Abstract: A semiconductor device and associated methods are disclosed. In one example, the electronic device includes a photonic die and a glass substrate. In selected examples, the semiconductor device includes one or more turning mirrors to direct an optical signal between the photonic die and the glass substrate. Configurations of turning mirrors are provided to improve signal integrity and manufacturability.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Bai Nie, Brandon C. Marin, Dingying Xu, Gang Duan, Hongxia Feng, Jeremy D. Ecton, Kristof Darmawikarta, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Xiaoying Guo, Yiqun Bai, Ziyin Lin
  • Publication number: 20240222298
    Abstract: Technologies for die recycling for high yield packaging is disclosed. In the illustrative embodiment, a release layer is deposited on one or more dies. The release layer includes conductive pads and a dielectric layer. Both the conductive pads and the dielectric layer have melting points between a temperature at which the die assembly will be processed and a temperature at which the die may sustain damage. One or more layers such as redistribution layers are deposited on the release layer. If a fault is discovered in the redistribution layers, the die assembly can be heated up past the melting point of the release layer, allowing the die to be removed. The die can then be cleaned and recycled for another packaging attempt.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Suddhasattwa Nad, Gang Duan
  • Publication number: 20240222249
    Abstract: In one embodiment, an integrated circuit package substrate includes a glass layer having at least one roughened surface (e.g., with an average roughness above 100 nm) and a metal (e.g., a metal trace or metal via) in contact with the roughened surface of the glass layer.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Srinivas V. Pietambaram, Gang Duan, Brandon Christian Marin, Suddhasattwa Nad, Oladeji T. Fadayomi, Manuel Gadogbe, Matthew L. Tingey
  • Publication number: 20240222257
    Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Ziyin Lin, Rahul N. Manepalli, Brandon C. Marin, Jeremy D. Ecton
  • Patent number: 12027466
    Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: July 2, 2024
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Aleksandar Aleksov, Brandon C. Marin, Yonggang Li, Leonel Arana, Suddhasattwa Nad, Haobo Chen, Tarek Ibrahim
  • Publication number: 20240213111
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. In an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. In an embodiment, the lid seals the channel between a first end and a second end of the channel.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Inventors: Mohammad Mamunur RAHMAN, Je-Young CHANG, Jeremy D. ECTON, Rahul N. MANEPALLI, Srinivas V. PIETAMBARAM, Gang DUAN, Brandon C. MARIN, Suddhasattwa NAD
  • Publication number: 20240213170
    Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
  • Publication number: 20240213169
    Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Bohan Shan, Haobo Chen, Yiqun Bai, Dingying Xu, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Kyle Jordan Arrington, Jeremy D. Ecton, Brandon C. Marin
  • Publication number: 20240203806
    Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: Bohan Shan, Bai Nie, Leonel R. Arana, Dingying XU, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Jeremy D. Ecton, Haobo Chen, Bin Mu
  • Publication number: 20240186227
    Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Kyle J. Arrington, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Hongxia Feng, Xiaoying Guo, Ziyin Lin, Brandon Christian Marin, Srinivas V. Pietambaram, Dingying Xu
  • Publication number: 20240186270
    Abstract: A microelectronic structure, a semiconductor package, an IC device assembly, and a method. The structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (TCVs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the TCVs; and a magnetic inductor (MI) within at least one of the core layer or the build-up layer and including an antiferromagnetic (AF) structure. The AF structure includes a first ferromagnetic (FM) layer; an exchange coupling (EC) layer on the first FM layer and including a non-magnetic metal material; a second FM layer on the EC layer, the EC layer between the first FM layer and the second FM layer; and a pinning (P) layer including manganese and at least one of platinum or iridium, the second FM layer between the EC layer and the P layer.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Claudio A. Alvarez Barros, Beomseok Choi, Gang Duan, Jeremy D. Ecton, Brandon Christian Marin, Suddhasattwa Nad, Hiroki Tanaka
  • Publication number: 20240186250
    Abstract: A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Brandon Christian Marin, Srinivas V. Pietambaram, Tarek A. Ibrahim, Suddhasattwa Nad, Gang Duan, Haobo Chen, Hiroki Tanaka
  • Publication number: 20240186228
    Abstract: In one embodiment, an integrated circuit package substrate includes a core layer comprising a dielectric material and a plurality of metal vias within the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus. The metal vias electrically couple a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a plurality of build-up layers on the core layer, the build-up layers comprising metal vias electrically connected to the metal vias of the core layer.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Intel Corporation
    Inventors: Haobo Chen, Bohan Shan, Kyle J. Arrington, Yiqun Bai, Kristof Darmawikarta, Gang Duan, Jeremy D. Ecton, Hongxia Feng, Xiaoying Guo, Ziyin Lin, Brandon Christian Marin, Bai Nie, Srinivas V. Pietambaram, Dingying Xu
  • Publication number: 20240178119
    Abstract: Embodiments disclosed herein include an interconnect. In an embodiment, the interconnect comprises a substrate and a pad over the substrate. In an embodiment, a hole is provided through the pad. In an embodiment, the hole exposes a portion of the substrate. In an embodiment, a solder is provided over the pad, and the solder bridges across the hole through the pad.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Mohammad Mamunur RAHMAN, Jeremy D. ECTON, Gang DUAN