Patents by Inventor Jeremy D. Ecton

Jeremy D. Ecton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230085646
    Abstract: An electronic device comprises a mold layer that includes multiple integrated circuit (IC) dice having contact pads, a glass core patch embedded in encapsulating material that surrounds the top, bottom, and sides of the glass core patch, and a first redistribution layer arranged between the first mold layer and the glass core patch. The first redistribution layer includes electrically conductive interconnect that electrically connects one or more contact pads of the IC dice to the glass core patch.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Jeremy D Ecton, Leonel R. Arana, Brandon C. Marin, Srinivas Venkata Ramanuja Pietambaram, Gang Duan
  • Publication number: 20230092242
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Srinivas V. PIETAMBARAM, Sameer PAITAL, Kristof DARMAWIKARTA, Hiroki TANAKA, Brandon C. MARIN, Jeremy D. ECTON, Gang DUAN
  • Publication number: 20230093258
    Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Jeremy D. ECTON, Srinivas V. PIETAMBARAM, Brandon C. MARIN, Haobo CHEN, Leonel ARANA
  • Publication number: 20230093008
    Abstract: Techniques for self-assembly of regions in a dielectric layer with different electrical properties are described herein. In one example, a package includes a substrate, a layer of dielectric material over the substrate, the layer of dielectric material including a filler material. The package includes a plurality of conductive traces in the layer of dielectric material, and a filler-depleted radial region of the dielectric material around each of the plurality of conductive traces. The filler-depleted radial region has a lower volume-percentage of filler than other regions of the layer of dielectric material. In one example, the conductive traces, filler, or both include a coating to cause the filler and traces to have opposing surface chemistry.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Brandon C. MARIN, Aleksandar ALEKSOV, Jeremy D. ECTON
  • Publication number: 20230087810
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD, Oscar OJEDA, Bai NIE, Brandon C. MARIN, Gang DUAN, Jacob VEHONSKY, Onur OZKAN, Nicholas S. HAEHN
  • Publication number: 20230077486
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first via is through the core, where the first via comprise a conductive material, and a film over the first surface of the core, where the film is an adhesive. In an embodiment, a second via is through the film, where the second via comprises a conductive material, where the second via contacts the first via. In an embodiment, a centerline of the second via is aligned with a centerline of the first via. In an embodiment, a buildup layer is over the film.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Aleksandar ALEKSOV, Srinivas V. PIETAMBARAM, Leonel ARANA
  • Publication number: 20230077633
    Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Changhua Liu, Pooya Tadayon, John Heck, Eric J. Moret, Tarek A. Ibrahim, Zhichao Zhang, Jeremy D Ecton
  • Publication number: 20230083425
    Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first sidewall and a second portion that includes a second sidewall, wherein the first sidewall includes seed metallization and the second sidewall excludes the seed metallization.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. Ecton, Darko Grujicic, Suddhasattwa Nad, Benjamin Duong
  • Publication number: 20230082385
    Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface, and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first width and a second portion having a second width different from the first width.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. Ecton, Kristof Darmawikarta, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Marcel Arlan Wall, Suddhasattwa Nad, Benjamin Duong, Rengarajan Shanmugam, Bai Nie, Helme Castro De La Torre
  • Publication number: 20230079607
    Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Suddhasattwa NAD, Leonel ARANA
  • Patent number: 11605867
    Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Jeremy D. Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Yonggang Li, Dilan Seneviratne
  • Publication number: 20230072096
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Hiroki Tanaka, Brandon C. Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D. Ecton, Rajeev Ranjan
  • Publication number: 20230076917
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Hiroki Tanaka, Brandon C. Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D. Ecton, Hari Mahalingam, Benjamin Duong
  • Publication number: 20230057384
    Abstract: Embodiments disclosed herein include carriers and methods of using the carriers to assemble electronic packages. In an embodiment, a carrier for electronic packaging assembly comprises a mold layer with a first surface and a second surface. In an embodiment, a plurality of glass substrates are embedded in the mold layer. In an embodiment, individual ones of the glass substrates comprise a third surface and a fourth surface, where the third surface of the glass substrate is substantially coplanar with the first surface of the mold layer.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Hiroki TANAKA, Jason M. GAMBA, Srinivas V. PIETAMBARAM
  • Publication number: 20220406654
    Abstract: Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity and low-photosensitivity photoresist are applied to a substrate and exposed at the same time with use of a dual-tone mask. After being developed, one photoresist forms an overhang over a sheltered region. The mold formed by the photoresists is filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the sheltered region forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Changhua Liu, Leonel R. Arana, Jeremy D. Ecton, Suddhasattwa Nad, Brandon Christian Marin
  • Publication number: 20220406618
    Abstract: Techniques for low- or zero-misaligned vias are disclosed. In one embodiment, a high-photosensitivity, medium-photosensitivity, and low-photosensitivity layer are applied to a substrate and exposed at the same time with use of a multi-tone mask. After being developed, one layer forms a mold for a first via, one layer forms a mold for a conductive trace and a second via, and one layer forms an overhang over the position for the second via. The molds formed by the photosensitive layers are filled with copper and then etched. The overhang prevents the top of the copper infill below the overhang region from being etched. As such, the region under the overhang forms a pillar or column after etching, which can be used as a via. Other embodiments are disclosed.
    Type: Application
    Filed: June 18, 2021
    Publication date: December 22, 2022
    Inventors: Changhua Liu, Leonel R. Arana, Jeremy D. Ecton, Suddhasattwa Nad, Brandon Christian Marin
  • Publication number: 20220310518
    Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Inventors: Haobo CHEN, Xiaoying GUO, Hongxia FENG, Kristof DARMAWIKARTA, Bai NIE, Tarek A. IBRAHIM, Gang DUAN, Jeremy D. ECTON, Sheng C. LI, Leonel ARANA
  • Publication number: 20220285278
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Inventors: Jeremy D. ECTON, Hiroki TANAKA, Oscar OJEDA, Arnab ROY, Vahidreza PARICHEHREH, Leonel R. ARANA, Chung Kwang TAN, Robert A. MAY
  • Patent number: 11373951
    Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Jeremy D. Ecton, Hiroki Tanaka, Oscar Ojeda, Arnab Roy, Vahidreza Parichehreh, Leonel R. Arana, Chung Kwang Tan, Robert A. May
  • Publication number: 20220196914
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Jeremy D. ECTON, Hiroki TANAKA, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Gang DUAN, Bai NIE, Haobo CHEN, Zhichao ZHANG, Sai VADLAMANI, Aleksandar ALEKSOV