Patents by Inventor Jeremy ECTON

Jeremy ECTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200258800
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Inventors: Jeremy ECTON, Oscar OJEDA, Leonel ARANA, Suddhasattwa NAD, Robert MAY, Hiroki TANAKA, Brandon C. MARIN
  • Publication number: 20200236795
    Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.
    Type: Application
    Filed: September 27, 2017
    Publication date: July 23, 2020
    Applicant: INTEL CORPORATION
    Inventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
  • Publication number: 20200205279
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the second thickness is different from the first thickness. In some embodiments, the first conductive trace and the second conductive trace have rectangular cross-sections.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Suddhasattwa Nad, Kristof Kuwawi Darmawikarta, Vahidreza Parichehreh, Veronica Aleman Strong, Xiaoying Guo
  • Publication number: 20200105685
    Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jeremy ECTON, Suddhasattwa NAD, Kristof DARMAWIKARTA, Yonggang LI, Xiaoying GUO
  • Patent number: 10515824
    Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Leonel Arana, Nicholas S. Haehn, Hsin-Wei Wang, Oscar Ojeda, Arnab Roy
  • Publication number: 20190378789
    Abstract: Embodiments may relate to a semiconductor package that includes a routing trace coupled with a substrate. The routing trace may be linear on a side of the routing trace between the substrate and a top of the routing trace. The semiconductor package may further include a power trace coupled with the substrate. The power trace may be concave on a side of the power trace between the substrate and a top of the power trace. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Applicant: Intel Corporation
    Inventor: Jeremy Ecton
  • Publication number: 20190304890
    Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Hiroki Tanaka, Kristof Kuwawi Darmawikarta, Oscar Ojeda, Arnab Roy, Nicholas Haehn
  • Publication number: 20190214272
    Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Jeremy ECTON, Leonel ARANA, Nicholas S. HAEHN, Hsin-Wei WANG, Oscar OJEDA, Arnab ROY